Cypress CY7C1268V18 TAP Controller State Diagram, State diagram for the TAP controller follows.9

Page 14

CY7C1266V18, CY7C1277V18

CY7C1268V18, CY7C1270V18

TAP Controller State Diagram

The state diagram for the TAP controller follows.[9]

1

0

TEST-LOGIC RESET

0

TEST-LOGIC/ IDLE

1

SELECT

1

1

SELECT

 

DR-SCAN

 

IR-SCAN

 

0

 

0

 

1

 

1

 

CAPTURE-DR

 

CAPTURE-IR

 

0

 

0

SHIFT-DR

 

0

SHIFT-IR

 

0

1

 

 

1

 

 

EXIT1-DR

 

1

EXIT1-IR

 

1

 

 

 

 

0

 

 

0

 

 

PAUSE-DR

0

PAUSE-IR

 

0

1

 

 

1

 

 

0

 

 

0

 

 

EXIT2-DR

 

 

EXIT2-IR

 

 

1

 

 

1

 

 

UPDATE-DR

 

UPDATE-IR

 

1

0

 

1

0

 

 

 

 

 

Note

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document Number: 001-06347 Rev. *D

Page 14 of 27

[+] Feedback

Image 14
Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1266V18 Logic Block Diagram CY7C1277V18Logic Block Diagram CY7C1268V18 Logic Block Diagram CY7C1270V18CY7C1277V18 4M x Pin ConfigurationsCY7C1266V18 4M x TMS TDIQvld CY7C1268V18 2M xCY7C1270V18 1M x BWSSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Negative Input Clock InputTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagFunctional Overview Truth Table Delay Lock Loop DLLApplication Example OperationRemains unaltered Write Cycle DescriptionsComments During the data portion of a write sequenceWritten into the device. D 359 remains unaltered Write cycle description table for CY7C1270V18 follows.2Into the device Into the device. D 80 and D 3518 remain unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller follows.9Parameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics GND ≤ VI ≤ VDDTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Waveforms Power Up Sequence in DDR-II+ SramPower Up Sequence DLL ConstraintsMaximum Ratings Electrical CharacteristicsDC Electrical Characteristics Operating RangeAC Test Loads and Waveforms Capacitance20Thermal Resistance20 Parameter Description Test Conditions Max UnitHigh Switching CharacteristicsParameter Min Max LOWNOP Switching WaveformsRead/Write/Deselect Sequence29 Ordering Information 333 Package Diagram Ball Fbga 15 x 17 x 1.40 mmNXR ECN No Issue Date Orig. Description of ChangeDocument History VKN