Cypress CY7C1277V18 TAP Controller Block Diagram, TAP Electrical Characteristics, Gnd ≤ Vi ≤ Vdd

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CY7C1266V18, CY7C1277V18

CY7C1268V18, CY7C1270V18

TAP Controller Block Diagram

0

Bypass Register

		Selection								Selection
		Circuitry								Circuitry
TDI		Circuitry			2		1	0		Circuitry
					2		1	0

			Instruction Register

31 30 29 . . 2 1 0

Identification Register

108 . . . . 2 1 0

Boundary Scan Register

TCK

TAP Controller

TMS

TAP Electrical Characteristics

Over the Operating Range[10, 11, 12]

TDO

Parameter	Description	Test Conditions	Min	Max	Unit
VOH1	Output HIGH Voltage	IOH = −2.0 mA	1.4		V
VOH2	Output HIGH Voltage	IOH = −100 μA	1.6		V
VOL1	Output LOW Voltage	IOL = 2.0 mA		0.4	V
VOL2	Output LOW Voltage	IOL = 100 μA		0.2	V
VIH	Input HIGH Voltage		0.65VDD	VDD + 0.3	V
VIL	Input LOW Voltage		–0.3	0.35VDD	V
IX	Input and OutputLoad Current	GND ≤ VI ≤ VDD	−5	5	μA

Notes

10.These characteristics apply to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in “Electrical Characteristics” on page 20.

11.Overshoot: VIH(AC) < VDDQ + 0.3V (pulse width less than tCYC/2). Undershoot: VIL(AC) > − 0.3V (pulse width less than tCYC/2).

12.All voltage refers to ground.

Document Number: 001-06347 Rev. *D

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1277V18 Logic Block Diagram CY7C1266V18Logic Block Diagram CY7C1270V18 Logic Block Diagram CY7C1268V18TMS TDI Pin ConfigurationsCY7C1266V18 4M x CY7C1277V18 4M xBWS CY7C1268V18 2M xCY7C1270V18 1M x QvldNegative Input Clock Input Pin DefinitionsPin Name Pin Description Synchronous Read/Write Input. WhenTCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Operation Delay Lock Loop DLLApplication Example Truth TableDuring the data portion of a write sequence Write Cycle DescriptionsComments Remains unalteredInto the device. D 80 and D 3518 remain unaltered Write cycle description table for CY7C1270V18 follows.2Into the device Written into the device. D 359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows.9 TAP Controller State DiagramGND ≤ VI ≤ VDD TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max UnitTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II+ SramPower Up Sequence Power Up WaveformsOperating Range Electrical CharacteristicsDC Electrical Characteristics Maximum RatingsParameter Description Test Conditions Max Unit Capacitance20Thermal Resistance20 AC Test Loads and WaveformsLOW Switching CharacteristicsParameter Min Max HighSwitching Waveforms Read/Write/Deselect Sequence29NOP Ordering Information 333 Ball Fbga 15 x 17 x 1.40 mm Package DiagramVKN ECN No Issue Date Orig. Description of ChangeDocument History NXR