Cypress CY7C1270V18, CY7C1266V18 Maximum Ratings, Operating Range, Electrical Characteristics

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CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature ................................ –65°C to + 150°C

Ambient Temperature with Power Applied. –55°C to + 125°C

Supply Voltage on VDD Relative to GND

–0.5V to + 2.9V

Supply Voltage on VDDQ Relative to GND

–0.5V to + VDD

DC Applied to Outputs in High-Z

–0.5V to VDDQ + 0.3V

DC Input Voltage[11]

–0.5V to V + 0.3V

 

 

DD

Current into Outputs (LOW)

20 mA

Static Discharge Voltage (MIL-STD-883, M 3015)....

>2001V

Latch up Current

>200 mA

Operating Range

 

Ambient

VDD[15]

VDDQ[15]

Range

Temperature

Com’l

0°C to +70°C

1.8 ± 0.1V

1.4V to VDD

Ind’l

–40°C to +85°C

 

 

 

 

 

 

Electrical Characteristics

Over the Operating Range[12]

DC Electrical Characteristics

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VDD

Power Supply Voltage

 

 

1.7

1.8

1.9

V

VDDQ

IO Supply Voltage

 

 

1.4

1.5

VDD

V

VOH

Output HIGH Voltage

Note 16

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOL

Output LOW Voltage

Note 17

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOH(LOW)

Output HIGH Voltage

IOH = –0.1 mA, Nominal Impedance

VDDQ – 0.2

 

VDDQ

V

VOL(LOW)

Output LOW Voltage

IOL = 0.1 mA, Nominal Impedance

VSS

 

0.2

V

VIH

Input HIGH Voltage

 

 

VREF + 0.1

 

VDDQ + 0.15

V

VIL

Input LOW Voltage

 

 

–0.15

 

VREF – 0.1

V

IX

Input Leakage Current

GND VI VDDQ

 

–2

 

2

μA

IOZ

Output Leakage Current

GND VI VDDQ, Output Disabled

–2

 

2

μA

VREF

Input Reference Voltage[18]

Typical Value = 0.75V

 

0.68

0.75

0.95

V

IDD [19]

VDD Operating Supply

VDD = Max., IOUT = 0 mA,

300 MHz

 

 

1000

mA

 

 

f = fMAX = 1/tCYC

 

 

 

 

 

 

 

333 MHz

 

 

1080

mA

 

 

 

375 MHz

 

 

1210

mA

 

 

 

 

 

 

 

 

 

 

 

400 MHz

 

 

1280

mA

 

 

 

 

 

 

 

 

ISB1

Automatic Power Down

Max. VDD,

300 MHz

 

 

290

mA

 

Current

Both Ports Deselected,

 

 

 

 

 

 

333 MHz

 

 

300

mA

 

 

VIN VIH or VIN VIL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

f = fMAX = 1/tCYC,

375 MHz

 

 

320

mA

 

 

Inputs Static

 

 

 

 

 

 

 

400 MHz

 

 

340

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

AC Input Requirements

Over the Operating Range [11]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VIH

Input HIGH Voltage

 

VREF + 0.2

VDDQ + 0.24

V

VIL

Input LOW Voltage

 

–0.24

VREF – 0.2

V

Notes

15.Power up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

16.Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

17.Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

18.VREF(min) = 0.68V or 0.46VDDQ, whichever is larger, VREF(max) = 0.95V or 0.54VDDQ, whichever is smaller.

19.The operation current is calculated with 50% read cycle and 50% write cycle.

Document Number: 001-06347 Rev. *D

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1266V18 Logic Block Diagram CY7C1277V18Logic Block Diagram CY7C1268V18 Logic Block Diagram CY7C1270V18Pin Configurations CY7C1266V18 4M xCY7C1277V18 4M x TMS TDICY7C1268V18 2M x CY7C1270V18 1M xQvld BWSPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Negative Input Clock InputPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Delay Lock Loop DLL Application ExampleTruth Table OperationWrite Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequenceWrite cycle description table for CY7C1270V18 follows.2 Into the deviceWritten into the device. D 359 remains unaltered Into the device. D 80 and D 3518 remain unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller follows.9TAP Controller Block Diagram TAP Electrical CharacteristicsParameter Description Test Conditions Min Max Unit GND ≤ VI ≤ VDDTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in DDR-II+ Sram Power Up SequencePower Up Waveforms DLL ConstraintsElectrical Characteristics DC Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance20 Thermal Resistance20AC Test Loads and Waveforms Parameter Description Test Conditions Max UnitSwitching Characteristics Parameter Min MaxHigh LOWNOP Switching WaveformsRead/Write/Deselect Sequence29 Ordering Information 333 Package Diagram Ball Fbga 15 x 17 x 1.40 mmECN No Issue Date Orig. Description of Change Document HistoryNXR VKN