Cypress CY7C67300 manual Power Savings and Reset Description, Power Saving Mode Description, Sleep

Page 13

CY7C67300

Minimum Hardware Requirements for Standalone Mode – Peripheral Only

Figure 9. Minimum Standalone Hardware Configuration – Peripheral Only

 

 

 

 

 

 

EZ-Host

 

 

 

 

 

 

 

CY7C67300

 

 

 

 

 

 

VReg

VCC, AVCC,

nRESET

Reset

 

 

 

 

 

Logic

 

 

 

 

 

 

BoostVCC

 

 

 

VBus

 

 

 

 

 

 

 

 

 

 

 

Standard-B

D+

 

 

 

DPlus

 

 

D-

 

 

 

DMinus

 

 

or Mini-B

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SHIELD

Bootstrap Options

 

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vcc

Vcc

 

 

47Kohm

 

 

 

 

 

 

 

 

 

10k

10k

 

Pin 38

 

 

 

 

 

 

 

 

 

 

 

 

GPIO[30]

SCL*

 

 

 

 

 

 

 

GPIO[31]

SDA*

 

 

 

 

 

 

 

 

Int. 16k x8

 

 

 

 

 

 

 

Code / Data

 

 

 

 

VCC

 

Bootloading Firmware

 

 

 

 

 

 

 

 

 

 

A0 Up to 64k x8

VCC

 

 

 

 

 

A1

EEPROM

WP

 

 

 

 

 

A2

 

 

SCL

 

 

Reserved

 

 

GND

 

 

SDA

 

 

 

22pf

 

 

 

 

 

XIN

 

 

 

 

 

 

GND, AGND,

 

 

 

 

 

 

 

 

12MHz

 

 

 

 

 

 

BoostGND

XOUT

 

 

 

 

 

 

 

 

22pf

 

 

 

 

 

 

 

 

*Bootloading begins after POR + 3ms BIOS bootup

 

* Parallel Resonant

*GPIO[31:30]

31

30

 

 

 

 

Fundamental Mode

 

 

 

 

500uW

Up to 2k x8

 

SCL

SDA

 

 

 

 

 

 

 

 

 

20-33pf ±5%

>2k x8 to 64k x8

SDA

SCL

 

 

 

 

 

 

 

 

 

Power Savings and Reset Description

This sections describes the different modes for resetting the chip and ways to save power.

Power Saving Mode Description

EZ-Host has one main power saving mode, Sleep. For detailed information about Sleep mode, see the Sleep section that follows.

Sleep mode is used for USB applications to support USB suspend and non USB applications as the main chip power down mode.

In addition, EZ-Host is capable of slowing down the CPU clock speed through the CPU Speed register [0xC008] without affecting other peripheral timing. Reducing the CPU clock speed from 48 MHz to 24 MHz reduces the overall current draw by around 8 mA while reducing it from 48 MHz to 3 MHz reduces the overall current draw by approximately 15 mA.

Sleep

Sleep mode is the main chip power down mode and is also used for USB suspend. Sleep mode is entered by setting the Sleep Enable (bit 1) of the Power control register [0xC00A]. During Sleep mode (USB Suspend) the following events and states are true:

■GPIO pins maintain their configuration during sleep (in suspend)

■External Memory address pins are driven low

■XTALOUT is turned off

■Internal PLL is turned off

■Ensure that firmware disables the charge pump (OTG Control register [0xC098]) thereby causing OTGVBUS to drop below 0.2V. Otherwise OTGVBUS only drops to VCC – (2 schottky diode drops).

■Booster circuit is turned off

■USB transceivers is turned off

■CPU goes into suspend mode until a programmable wakeup event

Document #: 38-08015 Rev. *J

Page 13 of 99

[+] Feedback

Page 12 Page 14
Image 13
Page 12 Page 14
Contents CY7C67300 Block Diagram EZ-Host FeaturesTypical Applications Functional Overview IntroductionInterface Descriptions USB Interface Interface Options for External Memory Bus Pins MEM PinsOTG Interface Pins Pin Name Pin Number USB Interface Pins Pin Name Pin NumberOTG Interface External Memory Interface External Memory Interface Pins Pin Name Pin Number External Memory Interface PinsExternal Memory Interface Block Diagrams Up to 256k x 16 External Code/Data Page ModeUart Interface General Purpose IO Interface GpioI2C Eeprom Interface Serial Peripheral InterfaceProgrammable Pulse/PWM Interface High-Speed Serial InterfaceHPI Interface Pins 3 HPI Interface Pins 3 Pin Name Pin NumberHost Port Interface IDE InterfaceIDE Interface Pins Pin Name Pin Number IDE Throughput ModeCharge Pump Interface Pins Pin Name Pin Number ActualCrystal Pins Booster PinsCrystal Pins Pin Name Pin Number Booster InterfaceBoot Configuration Interface Boot Configuration InterfaceBoot Mode Operational ModesPower Saving Mode Description Power Savings and Reset DescriptionSleep Memory Map Document # 38-08015 Rev. *JPage 15 Bank Selected 0xC018 0xC01AProcessor Control Registers RegistersBank Register Example Hex Value Binary Value Bank RegisterReserved Revision RegisterCPU Speed Definition Processor Speed Host/Device 2B Wake Enable Bit Power Control RegisterHost/Device 2A Wake Enable Bit Host/Device 1B Wake Enable BitInterrupt Enable Register Halt Enable Bit Sleep Enable BitOTG Interrupt Enable Bit SPI Interrupt Enable BitMailbox Interrupt Enable Bit HSS Interrupt Enable BitOut Mailbox Interrupt Enable Bit Uart Interrupt Enable BitPort 2B Diagnostic Enable Bit USB Diagnostic RegisterPort 2A Diagnostic Enable Bit Port 1B Diagnostic Enable BitExternal Memory Registers Upper Address Enable Bit Upper Address Enable Register 0xC038 R/WExtended Page n Map Register R/W Extended Page n Map RegisterTimer Registers Timeout Flag Bit Watchdog Timer RegisterLock Enable Bit WDT Enable BitGeneral USB Registers Timer n RegisterUSB n Control Register Port B D+ Status BitPort B Resistors Enable Bit Mode Select BitPort a Resistors Enable Bit EnablePreamble Enable Bit Port a SOF/EOP Enable Bit ReservedUSB Host Only Registers USB Host Only Register Register Name Address Host 1/HostHost n Address Register ISO Enable Bit Sync Enable BitArm Enable Bit Sequence Select BitUnderflow Flag Bit Port Select BitStall Flag Bit NAK Flag BitSequence Status Bit Error Flag BitHost n PID Register W Host n PID RegisterPID Select PID Select DefinitionHost n Count Result Register R Host n Count Result Register Endpoint Select BitsVbus Interrupt Enable Bit Host n Interrupt Enable RegisterID Interrupt Enable Bit Host n Device Address RegisterPort B Wake Interrupt Enable Bit SOF/EOP Interrupt Enable BitPort a Wake Interrupt Enable Bit Port B Connect Change Interrupt Enable BitPort B Wake Interrupt Flag Bit SOF/EOP Interrupt Flag BitPort a Wake Interrupt Flag Bit Port B Connect Change Interrupt Flag BitHost n SOF/EOP Counter Register Host n SOF/EOP Counter Register RHost n Frame Register R Host 1 Frame Register 0xC096 Host 2 Frame Register 0xC0B6USB Device Only Registers IN/OUT Ignore Enable BitDevice n Endpoint n Control Register R/W Device n Endpoint n Control RegisterNAK Interrupt Enable Bit Stall Enable BitEnable Bit Direction Select BitDevice n Endpoint n Count Register Device n Endpoint n Count Register R/WDevice n Endpoint n Status Register Device n Endpoint n Status Register R/WOUT Exception Flag Bit Exception Flag BitSequence Flag Bit Setup Flag BitDevice n Endpoint n Count Result Register R/W Device n Endpoint n Count Result RegisterDevice n Interrupt Enable Register Port Select Bit Device n Interrupt Enable Register R/WDevice n Port Select Register R/W Device n Port Select RegisterReset Interrupt Enable Bit SOF/EOP Timeout Interrupt Enable BitEP7 Interrupt Enable Bit EP6 Interrupt Enable BitDevice n Address Register W EP0 Interrupt Enable BitDevice n Address Register Device n Status Register R/WEP7 Interrupt Flag Bit Reset Interrupt Flag BitEP6 Interrupt Flag Bit EP5 Interrupt Flag BitSOF/EOP Timeout Interrupt Counter Bits SOF/EOP Timeout Flag BitEP2 Interrupt Flag Bit EP1 Interrupt Flag BitOTG Control Registers Vbus Pull-up Enable BitDevice n SOF/EOP Count Register OTG Control Register ReservedGpio Registers SAS Enable Bit Write Protect Enable BitMode Select Definition Gpio Configuration 108 HSS Enable BitInterrupt 0 Polarity Select Bit Reserved Interrupt 0 Enable BitGpio n Output Data Register Gpio n Input Data RegisterIDE Registers IDE Start Address Register 0xC04A R/W Mode Select DefinitionIDE Start Address Register IDE Enable Bit IDE Interrupt Enable BitIDE Stop Address Register IDE Control RegisterIDE PIO Port Registers 0xC050 0xC06F R/W HSS RegistersHSS Registers Register Name Address CTS Enable Bit Xoff Enable BitReceive Interrupt Enable Bit HSS Control RegisterTransmit Ready Bit Packet Mode Select BitReceive Overflow Flag Bit HSS Baud Rate RegisterHSS Transmit Gap Register HSS Transmit Gap Register 0xC074 R/WTransmit Gap Select Bits HSS Data Register 0xC076 R/WHSS Receive Counter Register HSS Receive Counter Register 0xC07A R/WHSS Transmit Address Register HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W HSS Transmit Counter RegisterHPI Registers Vbus to HPI Enable BitHPI Breakpoint Register HPI Registers Register Name Address Interrupt Routing RegisterSOF/EOP2 to HPI Enable Bit ID to HPI Enable BitSOF/EOP2 to CPU Enable Bit SOF/EOP1 to HPI Enable BitSIE1msg Register SIE2msg Register SIEXmsg Register WSIEXmsg Register HPI Mailbox Register 0xC0C6 R/WHPI Status Port Reset2 Flag BitVbus Flag Bit ID Flag BitSPI Registers Reset1 Flag BitDone1 Flag Bit Mailbox Out Flag BitPhase Select Bit 3Wire Enable BitMaster Active Enable Bit Master Enable BitRead Enable Bit Byte Mode BitSPI Control Register SCK Strobe BitTransmit Interrupt Enable Bit SPI Interrupt Enable RegisterTransfer Interrupt Enable Bit Fifo Error Flag BitTransmit Interrupt Flag Bit Receive Interrupt Flag BitSPI Interrupt Clear Register Transfer Interrupt Flag BitCRC Enable Bit CRC Mode Definition CRCMode CRC Polynomial 1514CRC Clear Bit SPI CRC Value Register Receive CRC BitSPI Data Register SPI Data Register 0xC0D6 R/WSPI Transmit Address Register 0xC0D8 R/W SPI Transmit Address RegisterSPI Receive Address Register SPI Transmit Count RegisterSPI Receive Count Register Uart Registers Uart Status Register Uart Status Register 0xC0E2 RReceive buffer full Receive buffer empty Uart Data Register 0xC0E4 R/WPWM Registers PWM Enable BitPWM Registers Register Name Address PWM Control RegisterPWM 2 Enable Bit PWM 3 Enable BitPWM 1 Enable Bit PWM 0 Enable BitPWM n Start Register PWM n Start Register R/WPWM n Stop Register R/W PWM n Stop RegisterPWM Cycle Count Register PWM Cycle Count Register 0xC0FA R/WPin Descriptions Pin DiagramPin Descriptions Name Type Mosi SPI Mosi D11/MOSISCK SPI SCK D8/MISOGPIO28/TX GPIO29/OTGIDGPIO27/RX GPIO26/CTS/PWM3Tie to Gnd for normal operation Booster Power input 2.7V toAbsolute Maximum Ratings DC CharacteristicsOperating Conditions Crystal Requirements XTALIN, XtaloutGND USB TransceiverReset Timing AC Timing CharacteristicsClock Timing Sram Read Cycle Parameters Description Min Typical Max Unit Sram Read Cycle15LOW Sram Write Cycle Parameters Sram Write CycleParameter Description Min Typical Max Unit HighSCL I2C Eeprom Timing-Serial IOSDA OUT HPI Host Port Interface Write Cycle Timing HPI Host Port Interface Read Cycle Timing Chip Select Hold Data Access Time, from HPInRD fallingRead Pulse Width Read Cycle TimeHSS Block Mode Transmit HSS Byte Mode TransmitHSS Byte and Block Mode Receive IDE TimingHardware CTS/RTS Handshake Register SummaryRegister Summary HSS SOF/EOP CRC SOF/EOP2 Ordering Information Package DiagramsOrdering Information Ordering Code Package Type Pb-FreeOrig. Submis Description of Change Sion Date Document HistoryWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB
Top Page Image Contents