Cypress CY7C67300 manual Memory Map

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CY7C67300

External (Remote) Wakeup Source

There are several possible events available to wake EZ-Host from Sleep mode as shown in Table 20. These may also be used as remote wakeup options for USB applications. See the Power Control Register [0xC00A] [R/W] on page 19 for details.

Upon wakeup, code begins executing within 200 µs, the time it takes the PLL to stabilize.

Table 20. Wakeup Sources[5, 6]

Wakeup Source

Event

(if enabled)

 

USB Resume

D+/D– Signaling

 

 

OTGVBUS

Level

 

 

OTGID

Any Edge

 

 

HPI

Read

 

 

HSS

Read

 

 

SPI

Read

 

 

IRQ1 (GPIO 25)

Any Edge

 

 

IRQ0 (GPIO 24)

Any Edge

 

 

Power-On-Reset Description

The length of the power-on-reset event can be defined by (VCC ramp to valid) + (Crystal startup). A typical application might use a 12 ms power-on-reset event = ~7 ms + ~5 ms, respectively.

Reset Pin

The Reset pin is active low and requires a minimum pulse duration of sixteen 12 MHz clock cycles (1.3 µs). A reset event restores all registers to their default POR settings. Code execution then begins 200 µs later at 0xFF00 with an immediate jump to 0xE000, the start of BIOS. Refer to BIOS documentation for additional details.

USB Reset

A USB Reset affects registers 0xC090 and 0xC0B0, all other registers remain unchanged.

Memory Map

The memory map is discussed in the following sections.

Mapping

The total memory space directly addressable by the CY16 processor is 64K (0x0000-0xFFFF). Program, data, and IO are contained within this 64K space. This memory space is byte addressable. Figure 10 on page 15 shows the various memory region address locations.

Internal Memory

Of the internal memory, 15K bytes are allocated for user's program and data. The lower memory space from 0x0000 to 0x04A2 is reserved for interrupt vectors, general purpose registers, USB control registers, stack, and other BIOS variables. The upper internal memory space contains EZ-Host control registers from 0xC000 to 0xC0FF and the BIOS ROM itself from 0xE000 to 0xFFFF. For more information about the reserved lower memory or the BIOS ROM, refer to the Programmer’s documentation and/or the BIOS documentation.

During development with the EZ-Host toolset, leave the lower area of user's space (0x04A4 to 0x1000) available to load the GDB stub. The GDB stub is required to allow the toolset debug access into EZ-Host.

The chip select pins are not active during accesses to internal memory.

External Memory

Up to 32 KB of external memory from 0x4000 - 0xBFFF is available via one chip select line (nXRAMSEL) with RAM Merge enabled (BIOS default). Additionally, another 8 KB region from 0xC100 - 0xDFFF is available via a second chip select line (nXROMSEL) giving 40 KB of total available external memory. Together with the internal 15 KB, this gives a total of either ~48 KB (one chip select) or ~56 KB (two chip selects) of available memory for either code or data.

Note that the memory map and pin names (nXRAMSEL/nXROMSEL) define specific memory regions for RAM vs. ROM. This allows the BIOS to look in the upper external memory space at 0xC100 for SCAN vectors (enabling code to be loaded/executed from ROM). If no SCAN vectors are required in the design (external memory is used exclusively for data), then all external memory regions can be used for RAM. Similarly, the external memory can be used exclusively for code space (ROM).

If more external memory is required, EZ-Host has enough address lines to support up to 512 KB. However, this requires complex code banking/paging schemes via the Extended Page registers.

For further information about setting up the external memory, see the External Memory Interface on page 5.

Notes

5.Read data is discarded (dummy data).

6.HPI_INT asserts on a USB Resume.

Document #: 38-08015 Rev. *J

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Contents Typical Applications EZ-Host FeaturesCY7C67300 Block Diagram Interface Descriptions IntroductionFunctional Overview Interface Options for External Memory Bus Pins MEM Pins USB InterfaceOTG Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number External Memory Interface External Memory Interface Block Diagrams External Memory Interface PinsExternal Memory Interface Pins Pin Name Pin Number Up to 256k x 16 External Code/Data Page ModeI2C Eeprom Interface General Purpose IO Interface GpioUart Interface Serial Peripheral InterfaceHigh-Speed Serial Interface Programmable Pulse/PWM InterfaceHost Port Interface HPI Interface Pins 3 Pin Name Pin NumberHPI Interface Pins 3 IDE InterfaceCharge Pump Interface Pins Pin Name Pin Number IDE Throughput ModeIDE Interface Pins Pin Name Pin Number ActualCrystal Pins Pin Name Pin Number Booster PinsCrystal Pins Booster InterfaceBoot Mode Boot Configuration InterfaceBoot Configuration Interface Operational ModesSleep Power Savings and Reset DescriptionPower Saving Mode Description Memory Map Bank Selected 0xC018 0xC01A Document # 38-08015 Rev. *JPage 15Registers Processor Control RegistersReserved Bank RegisterBank Register Example Hex Value Binary Value Revision RegisterCPU Speed Definition Processor Speed Host/Device 2A Wake Enable Bit Power Control RegisterHost/Device 2B Wake Enable Bit Host/Device 1B Wake Enable BitOTG Interrupt Enable Bit Sleep Enable BitInterrupt Enable Register Halt Enable Bit SPI Interrupt Enable BitOut Mailbox Interrupt Enable Bit HSS Interrupt Enable BitMailbox Interrupt Enable Bit Uart Interrupt Enable BitPort 2A Diagnostic Enable Bit USB Diagnostic RegisterPort 2B Diagnostic Enable Bit Port 1B Diagnostic Enable BitExternal Memory Registers Extended Page n Map Register R/W Upper Address Enable Register 0xC038 R/WUpper Address Enable Bit Extended Page n Map RegisterTimer Registers Lock Enable Bit Watchdog Timer RegisterTimeout Flag Bit WDT Enable BitUSB n Control Register Timer n RegisterGeneral USB Registers Port B D+ Status BitPort a Resistors Enable Bit Mode Select BitPort B Resistors Enable Bit EnableUSB Host Only Registers Port a SOF/EOP Enable Bit ReservedPreamble Enable Bit USB Host Only Register Register Name Address Host 1/HostArm Enable Bit Sync Enable BitHost n Address Register ISO Enable Bit Sequence Select BitStall Flag Bit Port Select BitUnderflow Flag Bit NAK Flag BitHost n PID Register W Error Flag BitSequence Status Bit Host n PID RegisterHost n Count Result Register R PID Select DefinitionPID Select Host n Count Result Register Endpoint Select BitsID Interrupt Enable Bit Host n Interrupt Enable RegisterVbus Interrupt Enable Bit Host n Device Address RegisterPort a Wake Interrupt Enable Bit SOF/EOP Interrupt Enable BitPort B Wake Interrupt Enable Bit Port B Connect Change Interrupt Enable BitPort a Wake Interrupt Flag Bit SOF/EOP Interrupt Flag BitPort B Wake Interrupt Flag Bit Port B Connect Change Interrupt Flag BitHost n Frame Register R Host n SOF/EOP Counter Register RHost n SOF/EOP Counter Register Host 1 Frame Register 0xC096 Host 2 Frame Register 0xC0B6Device n Endpoint n Control Register R/W IN/OUT Ignore Enable BitUSB Device Only Registers Device n Endpoint n Control RegisterEnable Bit Stall Enable BitNAK Interrupt Enable Bit Direction Select BitDevice n Endpoint n Count Register R/W Device n Endpoint n Count RegisterOUT Exception Flag Bit Device n Endpoint n Status Register R/WDevice n Endpoint n Status Register Exception Flag BitDevice n Endpoint n Count Result Register R/W Setup Flag BitSequence Flag Bit Device n Endpoint n Count Result RegisterDevice n Port Select Register R/W Device n Interrupt Enable Register R/WDevice n Interrupt Enable Register Port Select Bit Device n Port Select RegisterEP7 Interrupt Enable Bit SOF/EOP Timeout Interrupt Enable BitReset Interrupt Enable Bit EP6 Interrupt Enable BitDevice n Address Register EP0 Interrupt Enable BitDevice n Address Register W Device n Status Register R/WEP6 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP5 Interrupt Flag BitEP2 Interrupt Flag Bit SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits EP1 Interrupt Flag BitDevice n SOF/EOP Count Register Vbus Pull-up Enable BitOTG Control Registers OTG Control Register ReservedGpio Registers Mode Select Definition Gpio Configuration 108 Write Protect Enable BitSAS Enable Bit HSS Enable BitGpio n Output Data Register Interrupt 0 Enable BitInterrupt 0 Polarity Select Bit Reserved Gpio n Input Data RegisterIDE Registers IDE Start Address Register Mode Select DefinitionIDE Start Address Register 0xC04A R/W IDE Stop Address Register IDE Interrupt Enable BitIDE Enable Bit IDE Control RegisterHSS Registers Register Name Address HSS RegistersIDE PIO Port Registers 0xC050 0xC06F R/W Receive Interrupt Enable Bit Xoff Enable BitCTS Enable Bit HSS Control RegisterReceive Overflow Flag Bit Packet Mode Select BitTransmit Ready Bit HSS Baud Rate RegisterTransmit Gap Select Bits HSS Transmit Gap Register 0xC074 R/WHSS Transmit Gap Register HSS Data Register 0xC076 R/WHSS Receive Counter Register 0xC07A R/W HSS Receive Counter RegisterHSS Transmit Counter Register 0xC07E R/W HSS Transmit Address Register 0xC07C R/WHSS Transmit Address Register HSS Transmit Counter RegisterHPI Breakpoint Register HPI Registers Register Name Address Vbus to HPI Enable BitHPI Registers Interrupt Routing RegisterSOF/EOP2 to CPU Enable Bit ID to HPI Enable BitSOF/EOP2 to HPI Enable Bit SOF/EOP1 to HPI Enable BitSIEXmsg Register SIEXmsg Register WSIE1msg Register SIE2msg Register HPI Mailbox Register 0xC0C6 R/WVbus Flag Bit Reset2 Flag BitHPI Status Port ID Flag BitDone1 Flag Bit Reset1 Flag BitSPI Registers Mailbox Out Flag BitMaster Active Enable Bit 3Wire Enable BitPhase Select Bit Master Enable BitSPI Control Register Byte Mode BitRead Enable Bit SCK Strobe BitTransfer Interrupt Enable Bit SPI Interrupt Enable RegisterTransmit Interrupt Enable Bit Fifo Error Flag BitSPI Interrupt Clear Register Receive Interrupt Flag BitTransmit Interrupt Flag Bit Transfer Interrupt Flag BitCRC Clear Bit CRC Mode Definition CRCMode CRC Polynomial 1514CRC Enable Bit SPI CRC Value Register Receive CRC BitSPI Transmit Address Register 0xC0D8 R/W SPI Data Register 0xC0D6 R/WSPI Data Register SPI Transmit Address RegisterSPI Receive Count Register SPI Transmit Count RegisterSPI Receive Address Register Uart Registers Receive buffer full Receive buffer empty Uart Status Register 0xC0E2 RUart Status Register Uart Data Register 0xC0E4 R/WPWM Registers Register Name Address PWM Enable BitPWM Registers PWM Control RegisterPWM 1 Enable Bit PWM 3 Enable BitPWM 2 Enable Bit PWM 0 Enable BitPWM n Stop Register R/W PWM n Start Register R/WPWM n Start Register PWM n Stop RegisterPWM Cycle Count Register 0xC0FA R/W PWM Cycle Count RegisterPin Descriptions Name Type Pin DiagramPin Descriptions SCK SPI SCK D11/MOSIMosi SPI Mosi D8/MISOGPIO27/RX GPIO29/OTGIDGPIO28/TX GPIO26/CTS/PWM3Booster Power input 2.7V to Tie to Gnd for normal operationOperating Conditions DC CharacteristicsAbsolute Maximum Ratings Crystal Requirements XTALIN, XtaloutUSB Transceiver GNDClock Timing AC Timing CharacteristicsReset Timing LOW Sram Read Cycle15Sram Read Cycle Parameters Description Min Typical Max Unit Parameter Description Min Typical Max Unit Sram Write CycleSram Write Cycle Parameters HighSDA OUT I2C Eeprom Timing-Serial IOSCL HPI Host Port Interface Write Cycle Timing Read Pulse Width Chip Select Hold Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Cycle TimeHSS Byte and Block Mode Receive HSS Byte Mode TransmitHSS Block Mode Transmit IDE TimingRegister Summary Register SummaryHardware CTS/RTS Handshake HSS SOF/EOP CRC SOF/EOP2 Ordering Information Ordering Code Package Type Package DiagramsOrdering Information Pb-FreeDocument History Orig. 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