Cypress CY7C67300 manual Uart Status Register 0xC0E2 R, Receive buffer full Receive buffer empty

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																CY7C67300


UART Status Register [0xC0E2] [R]
Table 122. UART Status Register

Bit #	15	14			13			12			11		10		9		8
Field									Reserved...
Read/Write	-	-			-			-			-		-		-		-
Default	0	0			0			0			0		0		0		0

Bit #	7	6			5			4		3		2		1		0
Field					...Reserved									Receive Full			Transmit Full
Read/Write	-	-			-			-		-		-			R		R
Default	0	0			0			0		0		0		0		0

Register Description

The UART Status register is a read only register that indicates the status of the UART buffer.

Receive Full (Bit 1)

The Receive Full bit indicates whether the receive buffer is full. It can be programmed to interrupt the CPU as interrupt #5 when the buffer is full. This can be done though the UART bit of the Interrupt Enable register (0xC00E). This bit is automatically cleared when data is read from the UART Data register.

1:Receive buffer full

0:Receive buffer empty

UART Data Register [0xC0E4] [R/W]

Table 123. UART Data Register

Transmit Full (Bit 0)

The Transmit Full bit indicates whether the transmit buffer is full. It can be programmed to interrupt the CPU as interrupt #4 when the buffer is empty. This can be done though the UART bit of the Interrupt Enable register (0xC00E). This bit is automatically set to ‘1’ after data is written by EZ-Host to the UART Data register (to be transmitted). This bit is automatically cleared to ‘0’ after the data is transmitted.

1:Transmit buffer full (transmit busy)

0:Transmit buffer is empty and ready for a new byte of data

Bit #	15	14	13	12		11	10	9	8
Field					Reserved
Read/Write	-	-	-	-		-	-	-	-
Default	0	0	0	0		0	0	0	0

Bit #	7	6	5	4		3	2	1	0
Field					Data
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	0	0	0	0		0	0	0	0

Register Description

The UART Data register contains data to be transmitted or received from the UART port. Data written to this register starts a data transmission and also causes the UART Transmit Full Flag of the UART Status register to set. When data received on the UART port is read from this register, the UART Receive Full Flag of the UART Status register is cleared.

Data (Bits [7:0])

The Data field is where the UART data to be transmitted or received is located.

Reserved

Write all reserved bits with ’0’.

Document #: 38-08015 Rev. *J

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Contents Typical Applications EZ-Host FeaturesCY7C67300 Block Diagram Interface Descriptions IntroductionFunctional Overview Interface Options for External Memory Bus Pins MEM Pins USB InterfaceOTG Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number External Memory Interface External Memory Interface Block Diagrams External Memory Interface PinsExternal Memory Interface Pins Pin Name Pin Number Up to 256k x 16 External Code/Data Page ModeI2C Eeprom Interface General Purpose IO Interface GpioUart Interface Serial Peripheral InterfaceHigh-Speed Serial Interface Programmable Pulse/PWM InterfaceHost Port Interface HPI Interface Pins 3 Pin Name Pin NumberHPI Interface Pins 3 IDE InterfaceCharge Pump Interface Pins Pin Name Pin Number IDE Throughput ModeIDE Interface Pins Pin Name Pin Number ActualCrystal Pins Pin Name Pin Number Booster PinsCrystal Pins Booster InterfaceBoot Mode Boot Configuration InterfaceBoot Configuration Interface Operational ModesSleep Power Savings and Reset DescriptionPower Saving Mode Description Memory Map Bank Selected 0xC018 0xC01A Document # 38-08015 Rev. *JPage 15Registers Processor Control RegistersReserved Bank RegisterBank Register Example Hex Value Binary Value Revision RegisterCPU Speed Definition Processor Speed Host/Device 2A Wake Enable Bit Power Control RegisterHost/Device 2B Wake Enable Bit Host/Device 1B Wake Enable BitOTG Interrupt Enable Bit Sleep Enable BitInterrupt Enable Register Halt Enable Bit SPI Interrupt Enable BitOut Mailbox Interrupt Enable Bit HSS Interrupt Enable BitMailbox Interrupt Enable Bit Uart Interrupt Enable BitPort 2A Diagnostic Enable Bit USB Diagnostic RegisterPort 2B Diagnostic Enable Bit Port 1B Diagnostic Enable BitExternal Memory Registers Extended Page n Map Register R/W Upper Address Enable Register 0xC038 R/WUpper Address Enable Bit Extended Page n Map RegisterTimer Registers Lock Enable Bit Watchdog Timer RegisterTimeout Flag Bit WDT Enable BitUSB n Control Register Timer n RegisterGeneral USB Registers Port B D+ Status BitPort a Resistors Enable Bit Mode Select BitPort B Resistors Enable Bit EnableUSB Host Only Registers Port a SOF/EOP Enable Bit ReservedPreamble Enable Bit USB Host Only Register Register Name Address Host 1/HostArm Enable Bit Sync Enable BitHost n Address Register ISO Enable Bit Sequence Select BitStall Flag Bit Port Select BitUnderflow Flag Bit NAK Flag BitHost n PID Register W Error Flag BitSequence Status Bit Host n PID RegisterHost n Count Result Register R PID Select DefinitionPID Select Host n Count Result Register Endpoint Select BitsID Interrupt Enable Bit Host n Interrupt Enable RegisterVbus Interrupt Enable Bit Host n Device Address RegisterPort a Wake Interrupt Enable Bit SOF/EOP Interrupt Enable BitPort B Wake Interrupt Enable Bit Port B Connect Change Interrupt Enable BitPort a Wake Interrupt Flag Bit SOF/EOP Interrupt Flag BitPort B Wake Interrupt Flag Bit Port B Connect Change Interrupt Flag BitHost n Frame Register R Host n SOF/EOP Counter Register RHost n SOF/EOP Counter Register Host 1 Frame Register 0xC096 Host 2 Frame Register 0xC0B6Device n Endpoint n Control Register R/W IN/OUT Ignore Enable BitUSB Device Only Registers Device n Endpoint n Control RegisterEnable Bit Stall Enable BitNAK Interrupt Enable Bit Direction Select BitDevice n Endpoint n Count Register R/W Device n Endpoint n Count RegisterOUT Exception Flag Bit Device n Endpoint n Status Register R/WDevice n Endpoint n Status Register Exception Flag BitDevice n Endpoint n Count Result Register R/W Setup Flag BitSequence Flag Bit Device n Endpoint n Count Result RegisterDevice n Port Select Register R/W Device n Interrupt Enable Register R/WDevice n Interrupt Enable Register Port Select Bit Device n Port Select RegisterEP7 Interrupt Enable Bit SOF/EOP Timeout Interrupt Enable BitReset Interrupt Enable Bit EP6 Interrupt Enable BitDevice n Address Register EP0 Interrupt Enable BitDevice n Address Register W Device n Status Register R/WEP6 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP5 Interrupt Flag BitEP2 Interrupt Flag Bit SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits EP1 Interrupt Flag BitDevice n SOF/EOP Count Register Vbus Pull-up Enable BitOTG Control Registers OTG Control Register ReservedGpio Registers Mode Select Definition Gpio Configuration 108 Write Protect Enable BitSAS Enable Bit HSS Enable BitGpio n Output Data Register Interrupt 0 Enable BitInterrupt 0 Polarity Select Bit Reserved Gpio n Input Data RegisterIDE Registers IDE Start Address Register Mode Select DefinitionIDE Start Address Register 0xC04A R/W IDE Stop Address Register IDE Interrupt Enable BitIDE Enable Bit IDE Control RegisterHSS Registers Register Name Address HSS RegistersIDE PIO Port Registers 0xC050 0xC06F R/W Receive Interrupt Enable Bit Xoff Enable BitCTS Enable Bit HSS Control RegisterReceive Overflow Flag Bit Packet Mode Select BitTransmit Ready Bit HSS Baud Rate RegisterTransmit Gap Select Bits HSS Transmit Gap Register 0xC074 R/WHSS Transmit Gap Register HSS Data Register 0xC076 R/WHSS Receive Counter Register 0xC07A R/W HSS Receive Counter RegisterHSS Transmit Counter Register 0xC07E R/W HSS Transmit Address Register 0xC07C R/WHSS Transmit Address Register HSS Transmit Counter RegisterHPI Breakpoint Register HPI Registers Register Name Address Vbus to HPI Enable BitHPI Registers Interrupt Routing RegisterSOF/EOP2 to CPU Enable Bit ID to HPI Enable BitSOF/EOP2 to HPI Enable Bit SOF/EOP1 to HPI Enable BitSIEXmsg Register SIEXmsg Register WSIE1msg Register SIE2msg Register HPI Mailbox Register 0xC0C6 R/WVbus Flag Bit Reset2 Flag BitHPI Status Port ID Flag BitDone1 Flag Bit Reset1 Flag BitSPI Registers Mailbox Out Flag BitMaster Active Enable Bit 3Wire Enable BitPhase Select Bit Master Enable BitSPI Control Register Byte Mode BitRead Enable Bit SCK Strobe BitTransfer Interrupt Enable Bit SPI Interrupt Enable RegisterTransmit Interrupt Enable Bit Fifo Error Flag BitSPI Interrupt Clear Register Receive Interrupt Flag BitTransmit Interrupt Flag Bit Transfer Interrupt Flag BitCRC Clear Bit CRC Mode Definition CRCMode CRC Polynomial 1514CRC Enable Bit SPI CRC Value Register Receive CRC BitSPI Transmit Address Register 0xC0D8 R/W SPI Data Register 0xC0D6 R/WSPI Data Register SPI Transmit Address RegisterSPI Receive Count Register SPI Transmit Count RegisterSPI Receive Address Register Uart Registers Receive buffer full Receive buffer empty Uart Status Register 0xC0E2 RUart Status Register Uart Data Register 0xC0E4 R/WPWM Registers Register Name Address PWM Enable BitPWM Registers PWM Control RegisterPWM 1 Enable Bit PWM 3 Enable BitPWM 2 Enable Bit PWM 0 Enable BitPWM n Stop Register R/W PWM n Start Register R/WPWM n Start Register PWM n Stop RegisterPWM Cycle Count Register 0xC0FA R/W PWM Cycle Count RegisterPin Descriptions Name Type Pin DiagramPin Descriptions SCK SPI SCK D11/MOSIMosi SPI Mosi D8/MISOGPIO27/RX GPIO29/OTGIDGPIO28/TX GPIO26/CTS/PWM3Booster Power input 2.7V to Tie to Gnd for normal operationOperating Conditions DC CharacteristicsAbsolute Maximum Ratings Crystal Requirements XTALIN, XtaloutUSB Transceiver GNDClock Timing AC Timing CharacteristicsReset Timing LOW Sram Read Cycle15Sram Read Cycle Parameters Description Min Typical Max Unit Parameter Description Min Typical Max Unit Sram Write CycleSram Write Cycle Parameters HighSDA OUT I2C Eeprom Timing-Serial IOSCL HPI Host Port Interface Write Cycle Timing Read Pulse Width Chip Select Hold Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Cycle TimeHSS Byte and Block Mode Receive HSS Byte Mode TransmitHSS Block Mode Transmit IDE TimingRegister Summary Register SummaryHardware CTS/RTS Handshake HSS SOF/EOP CRC SOF/EOP2 Ordering Information Ordering Code Package Type Package DiagramsOrdering Information Pb-FreeDocument History Orig. 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