Cypress CY7C67300 manual IDE Timing, HSS Byte Mode Transmit, HSS Block Mode Transmit

Page 91

CY7C67300

IDE Timing

The IDE interface supports PIO mode 0-4 as specified in the Information Technology-AT Attachment–4 with Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18.

HSS BYTE Mode Transmit

qt_clk

CPU_A[2:0]

CPUHSS_cs

CPU_wr

TxRdy flag

HSS_TxD

CPU may start another BYTE transmit right after TxRdy goes high

BT BT

start bit

start bit

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

stop bit

Byte transmit triggered by a CPU write to the HSS_TxData register

TxRdy low to start bit delay:

0 min, BT max when starting from IDEL. For back to back transmit, new START Bit begins immediately following previous STOP bit.

(BT = bit period)

start of last data bit to TxRdy high: 0 min, 4 T max.

(T is qt_clk period)

programmable

1 or 2 stop bits.

1 stop bit shown.

qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate the relationship between CPU opera- tions and HSS port operations.

Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = data bit value ‘1’. BT = bit time = 1/baud rate.

HSS Block Mode Transmit

BT

HSS_TxD

t GAP

BLOCK mode transmit timing is similar to BYTE mode, except the STOP bit time is controlled by the HSS_GAP value.

The BLOCK mode STOP bit time, tGAP = (HSS_GAP – 9) BT, where BT is the bit time, and HSS_GAP is the content of the HSS Transmit Gap register [0xC074].

The default tGAP is 2 BT. BT = bit time = 1/baud rate.

HSS BYTE and BLOCK Mode Receive

HSS_RxD

BT +/- 5%							received byte added to
							received byte added to
	BT +/- 5%						receive FIFO during the final data bit time
start bit	bit 0	bit 1	bit 2	bit 3	bit 4	bit 5	bit 6	bit 7	stop bit	start bit
				10 BT +/- 5%

Receive data arrives asynchronously relative to the internal clock. Incoming data bit rate may deviate from the programmed baud rate clock by as much as ±5% (with HSS_RATE value of 23 or higher).

BYTE mode received bytes are buffered in a FIFO. The FIFO not empty condition becomes the RxRdy flag. BLOCK mode received bytes are written directly to the memory system.

Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_RxD HIGH = data bit value ‘1’. BT = bit time = 1/baud rate.

Document #: 38-08015 Rev. *J

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Contents CY7C67300 Block Diagram EZ-Host FeaturesTypical Applications Functional Overview IntroductionInterface Descriptions USB Interface Interface Options for External Memory Bus Pins MEM PinsOTG Interface Pins Pin Name Pin Number USB Interface Pins Pin Name Pin NumberOTG Interface External Memory Interface Up to 256k x 16 External Code/Data Page Mode External Memory Interface PinsExternal Memory Interface Pins Pin Name Pin Number External Memory Interface Block DiagramsSerial Peripheral Interface General Purpose IO Interface GpioUart Interface I2C Eeprom InterfaceProgrammable Pulse/PWM Interface High-Speed Serial InterfaceIDE Interface HPI Interface Pins 3 Pin Name Pin NumberHPI Interface Pins 3 Host Port InterfaceActual IDE Throughput ModeIDE Interface Pins Pin Name Pin Number Charge Pump Interface Pins Pin Name Pin NumberBooster Interface Booster PinsCrystal Pins Crystal Pins Pin Name Pin NumberOperational Modes Boot Configuration InterfaceBoot Configuration Interface Boot ModePower Saving Mode Description Power Savings and Reset DescriptionSleep Memory Map Document # 38-08015 Rev. *JPage 15 Bank Selected 0xC018 0xC01AProcessor Control Registers RegistersRevision Register Bank RegisterBank Register Example Hex Value Binary Value ReservedCPU Speed Definition Processor Speed Host/Device 1B Wake Enable Bit Power Control RegisterHost/Device 2B Wake Enable Bit Host/Device 2A Wake Enable BitSPI Interrupt Enable Bit Sleep Enable BitInterrupt Enable Register Halt Enable Bit OTG Interrupt Enable BitUart Interrupt Enable Bit HSS Interrupt Enable BitMailbox Interrupt Enable Bit Out Mailbox Interrupt Enable BitPort 1B Diagnostic Enable Bit USB Diagnostic RegisterPort 2B Diagnostic Enable Bit Port 2A Diagnostic Enable BitExternal Memory Registers Extended Page n Map Register Upper Address Enable Register 0xC038 R/WUpper Address Enable Bit Extended Page n Map Register R/WTimer Registers WDT Enable Bit Watchdog Timer RegisterTimeout Flag Bit Lock Enable BitPort B D+ Status Bit Timer n RegisterGeneral USB Registers USB n Control RegisterEnable Mode Select BitPort B Resistors Enable Bit Port a Resistors Enable BitUSB Host Only Register Register Name Address Host 1/Host Port a SOF/EOP Enable Bit ReservedPreamble Enable Bit USB Host Only RegistersSequence Select Bit Sync Enable BitHost n Address Register ISO Enable Bit Arm Enable BitNAK Flag Bit Port Select BitUnderflow Flag Bit Stall Flag BitHost n PID Register Error Flag BitSequence Status Bit Host n PID Register WHost n Count Result Register Endpoint Select Bits PID Select DefinitionPID Select Host n Count Result Register RHost n Device Address Register Host n Interrupt Enable RegisterVbus Interrupt Enable Bit ID Interrupt Enable BitPort B Connect Change Interrupt Enable Bit SOF/EOP Interrupt Enable BitPort B Wake Interrupt Enable Bit Port a Wake Interrupt Enable BitPort B Connect Change Interrupt Flag Bit SOF/EOP Interrupt Flag BitPort B Wake Interrupt Flag Bit Port a Wake Interrupt Flag BitHost 1 Frame Register 0xC096 Host 2 Frame Register 0xC0B6 Host n SOF/EOP Counter Register RHost n SOF/EOP Counter Register Host n Frame Register RDevice n Endpoint n Control Register IN/OUT Ignore Enable BitUSB Device Only Registers Device n Endpoint n Control Register R/WDirection Select Bit Stall Enable BitNAK Interrupt Enable Bit Enable BitDevice n Endpoint n Count Register Device n Endpoint n Count Register R/WException Flag Bit Device n Endpoint n Status Register R/WDevice n Endpoint n Status Register OUT Exception Flag BitDevice n Endpoint n Count Result Register Setup Flag BitSequence Flag Bit Device n Endpoint n Count Result Register R/WDevice n Port Select Register Device n Interrupt Enable Register R/WDevice n Interrupt Enable Register Port Select Bit Device n Port Select Register R/WEP6 Interrupt Enable Bit SOF/EOP Timeout Interrupt Enable BitReset Interrupt Enable Bit EP7 Interrupt Enable BitDevice n Status Register R/W EP0 Interrupt Enable BitDevice n Address Register W Device n Address RegisterEP5 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP6 Interrupt Flag BitEP1 Interrupt Flag Bit SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits EP2 Interrupt Flag BitOTG Control Register Reserved Vbus Pull-up Enable BitOTG Control Registers Device n SOF/EOP Count RegisterGpio Registers HSS Enable Bit Write Protect Enable BitSAS Enable Bit Mode Select Definition Gpio Configuration 108Gpio n Input Data Register Interrupt 0 Enable BitInterrupt 0 Polarity Select Bit Reserved Gpio n Output Data RegisterIDE Registers IDE Start Address Register 0xC04A R/W Mode Select DefinitionIDE Start Address Register IDE Control Register IDE Interrupt Enable BitIDE Enable Bit IDE Stop Address RegisterIDE PIO Port Registers 0xC050 0xC06F R/W HSS RegistersHSS Registers Register Name Address HSS Control Register Xoff Enable BitCTS Enable Bit Receive Interrupt Enable BitHSS Baud Rate Register Packet Mode Select BitTransmit Ready Bit Receive Overflow Flag BitHSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WHSS Transmit Gap Register Transmit Gap Select BitsHSS Receive Counter Register HSS Receive Counter Register 0xC07A R/WHSS Transmit Counter Register HSS Transmit Address Register 0xC07C R/WHSS Transmit Address Register HSS Transmit Counter Register 0xC07E R/WInterrupt Routing Register Vbus to HPI Enable BitHPI Registers HPI Breakpoint Register HPI Registers Register Name AddressSOF/EOP1 to HPI Enable Bit ID to HPI Enable BitSOF/EOP2 to HPI Enable Bit SOF/EOP2 to CPU Enable BitHPI Mailbox Register 0xC0C6 R/W SIEXmsg Register WSIE1msg Register SIE2msg Register SIEXmsg RegisterID Flag Bit Reset2 Flag BitHPI Status Port Vbus Flag BitMailbox Out Flag Bit Reset1 Flag BitSPI Registers Done1 Flag BitMaster Enable Bit 3Wire Enable BitPhase Select Bit Master Active Enable BitSCK Strobe Bit Byte Mode BitRead Enable Bit SPI Control RegisterFifo Error Flag Bit SPI Interrupt Enable RegisterTransmit Interrupt Enable Bit Transfer Interrupt Enable BitTransfer Interrupt Flag Bit Receive Interrupt Flag BitTransmit Interrupt Flag Bit SPI Interrupt Clear RegisterSPI CRC Value Register Receive CRC Bit CRC Mode Definition CRCMode CRC Polynomial 1514CRC Enable Bit CRC Clear BitSPI Transmit Address Register SPI Data Register 0xC0D6 R/WSPI Data Register SPI Transmit Address Register 0xC0D8 R/WSPI Receive Address Register SPI Transmit Count RegisterSPI Receive Count Register Uart Registers Uart Data Register 0xC0E4 R/W Uart Status Register 0xC0E2 RUart Status Register Receive buffer full Receive buffer emptyPWM Control Register PWM Enable BitPWM Registers PWM Registers Register Name AddressPWM 0 Enable Bit PWM 3 Enable BitPWM 2 Enable Bit PWM 1 Enable BitPWM n Stop Register PWM n Start Register R/WPWM n Start Register PWM n Stop Register R/WPWM Cycle Count Register PWM Cycle Count Register 0xC0FA R/WPin Descriptions Pin DiagramPin Descriptions Name Type D8/MISO D11/MOSIMosi SPI Mosi SCK SPI SCKGPIO26/CTS/PWM3 GPIO29/OTGIDGPIO28/TX GPIO27/RXTie to Gnd for normal operation Booster Power input 2.7V toCrystal Requirements XTALIN, Xtalout DC CharacteristicsAbsolute Maximum Ratings Operating ConditionsGND USB TransceiverReset Timing AC Timing CharacteristicsClock Timing Sram Read Cycle Parameters Description Min Typical Max Unit Sram Read Cycle15LOW High Sram Write CycleSram Write Cycle Parameters Parameter Description Min Typical Max UnitSCL I2C Eeprom Timing-Serial IOSDA OUT HPI Host Port Interface Write Cycle Timing Read Cycle Time Chip Select Hold Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Pulse WidthIDE Timing HSS Byte Mode TransmitHSS Block Mode Transmit HSS Byte and Block Mode ReceiveHardware CTS/RTS Handshake Register SummaryRegister Summary HSS SOF/EOP CRC SOF/EOP2 Pb-Free Package DiagramsOrdering Information Ordering Information Ordering Code Package TypeOrig. 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