Cypress CY7C67300 manual Stall Enable Bit, NAK Interrupt Enable Bit, Direction Select Bit

Page 39

CY7C67300

Sequence Select (Bit 6)

The Sequence Select bit determines whether a DATA0 or a DATA1 is sent for the next data toggle. This bit has no effect on receiving data packets; sequence checking must be handled in firmware.

1:Send a DATA1

0:Send a DATA0

Stall Enable (Bit 5)

The Stall Enable bit sends a Stall in response to the next request (unless it is a setup request, which are always ACKed). This is a sticky bit and continues to respond with Stalls until cleared by firmware.

1:Send Stall

0:Do not send Stall

ISO Enable (Bit 4)

The ISO Enable bit enables and disables an isochronous trans- action. This bit is only valid for EPs 1–7 and has no function for EP0.

1:Enable isochronous transaction

0:Disable isochronous transaction

NAK Interrupt Enable (Bit 3)

The NAK Interrupt Enable bit enables and disables the gener- ation of an Endpoint n interrupt when the device responds to the host with a NAK. The Endpoint n Interrupt Enable bit in the Device n Interrupt Enable register must also be set. When a NAK is sent to the host, the corresponding EP Interrupt Flag in the Device n Status register is set. In addition, the NAK Flag in the Device n Endpoint n Status register is set.

1:Enable NAK interrupt

0:Disable NAK interrupt

Device n Endpoint n Address Register [R/W]

Direction Select (Bit 2)

The Direction Select bit needs to be set according to the expected direction of the next data stage in the next transaction. If the data stage direction is different from what is set in this bit, it gets NAKed and either the IN Exception Flag or the OUT Exception Flag is set in the Device n Endpoint n Status register. If a setup packet is received and the Direction Select bit is set incorrectly, the setup is ACKed and the Setup Status Flag is set (refer to the setup bit of the Device n Endpoint n Status Register [R/W] on page 41 for details).

1:OUT transfer (host to device)

0:IN transfer (device to host)

Enable (Bit 1)

Set the Enable bit to allow transfers to the endpoint. If Enable is set to ‘0’ then all USB traffic to this endpoint is ignored. If Enable is set ‘1’ and Arm Enable (bit 0) is set ‘0’ then NAKs are automat- ically returned from this endpoint (except setup packets which are always ACKed as long as the Enable bit is set).

1:Enable transfers to an endpoint

0:Do not allow transfers to an endpoint

Arm Enable (Bit 0)

The Arm Enable bit arms the endpoint to transfer or receive a packet. This bit is cleared to ‘0’ when a transaction is complete.

1:Arm endpoint

0:Endpoint disarmed

Reserved

Write all reserved bits with ’0’.

■Device n Endpoint 0 Address Register [Device 1: 0x0202 Device 2: 0x0282]

■Device n Endpoint 1 Address Register [Device 1: 0x0212 Device 2: 0x0292]

■Device n Endpoint 2 Address Register [Device 1: 0x0222 Device 2: 0x02A2]

■Device n Endpoint 3 Address Register [Device 1: 0x0232 Device 2: 0x02B2]

■Device n Endpoint 4 Address Register [Device 1: 0x0242 Device 2: 0x02C2]

■Device n Endpoint 5 Address Register [Device 1: 0x0252 Device 2: 0x02D2]

■Device n Endpoint 6 Address Register [Device 1: 0x0262 Device 2: 0x02E2]

■Device n Endpoint 7 Address Register [Device 1: 0x0272 Device 2: 0x02F2]

Table 64. Device n Endpoint n Address Register

Bit #

15

14

13

12

 

11

10

9

8

Field

 

 

 

 

Address...

 

 

 

Read/Write

R/W

R/W

R/W

R/W

 

R/W

R/W

R/W

R/W

Default

X

X

X

X

 

X

X

X

X

Bit #

7

6

5

4

 

3

2

1

0

Field

 

 

 

 

...Address

 

 

 

Read/Write

R/W

R/W

R/W

R/W

 

R/W

R/W

R/W

R/W

Default

X

X

X

X

 

X

X

X

X

Document #: 38-08015 Rev. *J

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Contents EZ-Host Features CY7C67300 Block DiagramTypical Applications Introduction Functional OverviewInterface Descriptions USB Interface Interface Options for External Memory Bus Pins MEM PinsUSB Interface Pins Pin Name Pin Number OTG Interface Pins Pin Name Pin NumberOTG Interface External Memory Interface Up to 256k x 16 External Code/Data Page Mode External Memory Interface PinsExternal Memory Interface Pins Pin Name Pin Number External Memory Interface Block DiagramsSerial Peripheral Interface General Purpose IO Interface GpioUart Interface I2C Eeprom InterfaceProgrammable Pulse/PWM Interface High-Speed Serial InterfaceIDE Interface HPI Interface Pins 3 Pin Name Pin NumberHPI Interface Pins 3 Host Port InterfaceActual IDE Throughput ModeIDE Interface Pins Pin Name Pin Number Charge Pump Interface Pins Pin Name Pin NumberBooster Interface Booster PinsCrystal Pins Crystal Pins Pin Name Pin NumberOperational Modes Boot Configuration InterfaceBoot Configuration Interface Boot ModePower Savings and Reset Description Power Saving Mode DescriptionSleep Memory Map Document # 38-08015 Rev. *JPage 15 Bank Selected 0xC018 0xC01AProcessor Control Registers RegistersRevision Register Bank RegisterBank Register Example Hex Value Binary Value ReservedCPU Speed Definition Processor Speed Host/Device 1B Wake Enable Bit Power Control RegisterHost/Device 2B Wake Enable Bit Host/Device 2A Wake Enable BitSPI Interrupt Enable Bit Sleep Enable BitInterrupt Enable Register Halt Enable Bit OTG Interrupt Enable BitUart Interrupt Enable Bit HSS Interrupt Enable BitMailbox Interrupt Enable Bit Out Mailbox Interrupt Enable BitPort 1B Diagnostic Enable Bit USB Diagnostic RegisterPort 2B Diagnostic Enable Bit Port 2A Diagnostic Enable BitExternal Memory Registers Extended Page n Map Register Upper Address Enable Register 0xC038 R/WUpper Address Enable Bit Extended Page n Map Register R/WTimer Registers WDT Enable Bit Watchdog Timer RegisterTimeout Flag Bit Lock Enable BitPort B D+ Status Bit Timer n RegisterGeneral USB Registers USB n Control RegisterEnable Mode Select BitPort B Resistors Enable Bit Port a Resistors Enable BitUSB Host Only Register Register Name Address Host 1/Host Port a SOF/EOP Enable Bit ReservedPreamble Enable Bit USB Host Only RegistersSequence Select Bit Sync Enable BitHost n Address Register ISO Enable Bit Arm Enable BitNAK Flag Bit Port Select BitUnderflow Flag Bit Stall Flag BitHost n PID Register Error Flag BitSequence Status Bit Host n PID Register WHost n Count Result Register Endpoint Select Bits PID Select DefinitionPID Select Host n Count Result Register RHost n Device Address Register Host n Interrupt Enable RegisterVbus Interrupt Enable Bit ID Interrupt Enable BitPort B Connect Change Interrupt Enable Bit SOF/EOP Interrupt Enable BitPort B Wake Interrupt Enable Bit Port a Wake Interrupt Enable BitPort B Connect Change Interrupt Flag Bit SOF/EOP Interrupt Flag BitPort B Wake Interrupt Flag Bit Port a Wake Interrupt Flag BitHost 1 Frame Register 0xC096 Host 2 Frame Register 0xC0B6 Host n SOF/EOP Counter Register RHost n SOF/EOP Counter Register Host n Frame Register RDevice n Endpoint n Control Register IN/OUT Ignore Enable BitUSB Device Only Registers Device n Endpoint n Control Register R/WDirection Select Bit Stall Enable BitNAK Interrupt Enable Bit Enable BitDevice n Endpoint n Count Register Device n Endpoint n Count Register R/WException Flag Bit Device n Endpoint n Status Register R/WDevice n Endpoint n Status Register OUT Exception Flag BitDevice n Endpoint n Count Result Register Setup Flag BitSequence Flag Bit Device n Endpoint n Count Result Register R/WDevice n Port Select Register Device n Interrupt Enable Register R/WDevice n Interrupt Enable Register Port Select Bit Device n Port Select Register R/WEP6 Interrupt Enable Bit SOF/EOP Timeout Interrupt Enable BitReset Interrupt Enable Bit EP7 Interrupt Enable BitDevice n Status Register R/W EP0 Interrupt Enable BitDevice n Address Register W Device n Address RegisterEP5 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP6 Interrupt Flag BitEP1 Interrupt Flag Bit SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits EP2 Interrupt Flag BitOTG Control Register Reserved Vbus Pull-up Enable BitOTG Control Registers Device n SOF/EOP Count RegisterGpio Registers HSS Enable Bit Write Protect Enable BitSAS Enable Bit Mode Select Definition Gpio Configuration 108Gpio n Input Data Register Interrupt 0 Enable BitInterrupt 0 Polarity Select Bit Reserved Gpio n Output Data RegisterIDE Registers Mode Select Definition IDE Start Address Register 0xC04A R/WIDE Start Address Register IDE Control Register IDE Interrupt Enable BitIDE Enable Bit IDE Stop Address RegisterHSS Registers IDE PIO Port Registers 0xC050 0xC06F R/WHSS Registers Register Name Address HSS Control Register Xoff Enable BitCTS Enable Bit Receive Interrupt Enable BitHSS Baud Rate Register Packet Mode Select BitTransmit Ready Bit Receive Overflow Flag BitHSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WHSS Transmit Gap Register Transmit Gap Select BitsHSS Receive Counter Register HSS Receive Counter Register 0xC07A R/WHSS Transmit Counter Register HSS Transmit Address Register 0xC07C R/WHSS Transmit Address Register HSS Transmit Counter Register 0xC07E R/WInterrupt Routing Register Vbus to HPI Enable BitHPI Registers HPI Breakpoint Register HPI Registers Register Name AddressSOF/EOP1 to HPI Enable Bit ID to HPI Enable BitSOF/EOP2 to HPI Enable Bit SOF/EOP2 to CPU Enable BitHPI Mailbox Register 0xC0C6 R/W SIEXmsg Register WSIE1msg Register SIE2msg Register SIEXmsg RegisterID Flag Bit Reset2 Flag BitHPI Status Port Vbus Flag BitMailbox Out Flag Bit Reset1 Flag BitSPI Registers Done1 Flag BitMaster Enable Bit 3Wire Enable BitPhase Select Bit Master Active Enable BitSCK Strobe Bit Byte Mode BitRead Enable Bit SPI Control RegisterFifo Error Flag Bit SPI Interrupt Enable RegisterTransmit Interrupt Enable Bit Transfer Interrupt Enable BitTransfer Interrupt Flag Bit Receive Interrupt Flag BitTransmit Interrupt Flag Bit SPI Interrupt Clear RegisterSPI CRC Value Register Receive CRC Bit CRC Mode Definition CRCMode CRC Polynomial 1514CRC Enable Bit CRC Clear BitSPI Transmit Address Register SPI Data Register 0xC0D6 R/WSPI Data Register SPI Transmit Address Register 0xC0D8 R/WSPI Transmit Count Register SPI Receive Address RegisterSPI Receive Count Register Uart Registers Uart Data Register 0xC0E4 R/W Uart Status Register 0xC0E2 RUart Status Register Receive buffer full Receive buffer emptyPWM Control Register PWM Enable BitPWM Registers PWM Registers Register Name AddressPWM 0 Enable Bit PWM 3 Enable BitPWM 2 Enable Bit PWM 1 Enable BitPWM n Stop Register PWM n Start Register R/WPWM n Start Register PWM n Stop Register R/WPWM Cycle Count Register PWM Cycle Count Register 0xC0FA R/WPin Diagram Pin DescriptionsPin Descriptions Name Type D8/MISO D11/MOSIMosi SPI Mosi SCK SPI SCKGPIO26/CTS/PWM3 GPIO29/OTGIDGPIO28/TX GPIO27/RXTie to Gnd for normal operation Booster Power input 2.7V toCrystal Requirements XTALIN, Xtalout DC CharacteristicsAbsolute Maximum Ratings Operating ConditionsGND USB TransceiverAC Timing Characteristics Reset TimingClock Timing Sram Read Cycle15 Sram Read Cycle Parameters Description Min Typical Max UnitLOW High Sram Write CycleSram Write Cycle Parameters Parameter Description Min Typical Max UnitI2C Eeprom Timing-Serial IO SCLSDA OUT HPI Host Port Interface Write Cycle Timing Read Cycle Time Chip Select Hold Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Pulse WidthIDE Timing HSS Byte Mode TransmitHSS Block Mode Transmit HSS Byte and Block Mode ReceiveRegister Summary Hardware CTS/RTS HandshakeRegister Summary HSS SOF/EOP CRC SOF/EOP2 Pb-Free Package DiagramsOrdering Information Ordering Information Ordering Code Package TypeOrig. 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