Cypress CY7C67300 USB Diagnostic Register, Port 2B Diagnostic Enable Bit, Pull-down Enable Bit

Page 22

 

 

 

 

 

 

 

 

 

 

CY7C67300

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

USB Diagnostic Register [0xC03C] [R/W]

 

 

 

 

 

 

 

 

 

Table 31. USB Diagnostic Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit #

15

14

13

12

11

10

9

 

8

 

 

 

Port 2B

Port 2A

Port 1B

Port 1A

 

Reserved...

 

 

 

 

Field

Diagnostic

Diagnostic

Diagnostic

Diagnostic

 

 

 

 

 

 

 

Enable

Enable

Enable

Enable

 

 

 

 

 

 

 

Read/Write

R/W

 

 

R/W

R/W

R/W

-

-

-

 

-

 

 

Default

0

0

0

0

0

0

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit #

7

6

5

4

3

2

1

 

0

 

 

Field

...Reserved

Pull-down

LS Pull-up

FS Pull-up

Reserved

 

Force Select

 

 

 

 

 

Enable

Enable

Enable

 

 

 

 

 

 

 

Read/Write

-

 

 

R/W

R/W

R/W

-

R/W

R/W

 

R/W

 

 

Default

0

0

0

0

0

0

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register Description

The USB Diagnostic register provides control of diagnostic modes. It is intended for use by device characterization tests, not for normal operations. This register is read/write by the on-chip CPU but is write-only via the HPI port.

Port 2B Diagnostic Enable (Bit 15)

The Port 2B Diagnostic Enable bit enables or disables Port 2B for the test conditions selected in this register.

1:Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD

0:Do not apply test conditions

Port 2A Diagnostic Enable (Bit 14)

The Port 2A Diagnostic Enable bit enables or disables Port 2A for the test conditions selected in this register.

1:Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD

0:Do not apply test conditions

Port 1B Diagnostic Enable (Bit 13)

The Port 1B Diagnostic Enable bit enables or disables Port 1B for the test conditions selected in this register.

1:Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD

0:Do not apply test conditions

Port 1A Diagnostic Enable (Bit 12)

The Port 1A Diagnostic Enable bit enables or disables Port 1A for the test conditions selected in this register.

1:Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD

0:Do not apply test conditions

Pull-down Enable (Bit 6)

The Pull-down Enable bit enables or disables full-speed pull down resistors (pull down on both D+ and D–) for testing.

1:Enable pull down resistors on both D+ and D–

0:Disable pull down resistors on both D+ and D–

LS Pull-up Enable (Bit 5)

The LS Pull-up Enable bit enables or disables a low-speed pull up resistor (pull up on D–) for testing.

1:Enable low-speed pull up resistor on D–

0:Pull-up resistor is not connected on D–

FS Pull-up Enable (Bit 4)

The FS Pull-up Enable bit enables or disables a full-speed pull up resistor (pull up on D+) for testing.

1:Enable full-speed pull up resistor on D+

0:Pull up resistor is not connected on D+

Force Select (Bits [2:0])

The Force Select field bit selects several different test condition states on the data lines (D+/D–). Refer to Table 32 for details.

Table 32. Force Select Definition

Force Select [2:0]

 

Data Line State

1xx

 

Assert SE0

 

 

 

01x

 

Toggle JK

 

 

 

001

 

Assert J

 

 

 

000

 

Assert K

 

 

 

Reserved

 

Write all reserved bits with ’0’.

 

Document #: 38-08015 Rev. *J

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Contents CY7C67300 Block Diagram EZ-Host FeaturesTypical Applications Functional Overview IntroductionInterface Descriptions Interface Options for External Memory Bus Pins MEM Pins USB InterfaceOTG Interface Pins Pin Name Pin Number USB Interface Pins Pin Name Pin NumberOTG Interface External Memory Interface External Memory Interface Block Diagrams External Memory Interface PinsExternal Memory Interface Pins Pin Name Pin Number Up to 256k x 16 External Code/Data Page ModeI2C Eeprom Interface General Purpose IO Interface GpioUart Interface Serial Peripheral InterfaceHigh-Speed Serial Interface Programmable Pulse/PWM InterfaceHost Port Interface HPI Interface Pins 3 Pin Name Pin NumberHPI Interface Pins 3 IDE InterfaceCharge Pump Interface Pins Pin Name Pin Number IDE Throughput ModeIDE Interface Pins Pin Name Pin Number ActualCrystal Pins Pin Name Pin Number Booster PinsCrystal Pins Booster InterfaceBoot Mode Boot Configuration InterfaceBoot Configuration Interface Operational ModesPower Saving Mode Description Power Savings and Reset DescriptionSleep Memory Map Bank Selected 0xC018 0xC01A Document # 38-08015 Rev. *JPage 15Registers Processor Control RegistersReserved Bank RegisterBank Register Example Hex Value Binary Value Revision RegisterCPU Speed Definition Processor Speed Host/Device 2A Wake Enable Bit Power Control RegisterHost/Device 2B Wake Enable Bit Host/Device 1B Wake Enable BitOTG Interrupt Enable Bit Sleep Enable BitInterrupt Enable Register Halt Enable Bit SPI Interrupt Enable BitOut Mailbox Interrupt Enable Bit HSS Interrupt Enable BitMailbox Interrupt Enable Bit Uart Interrupt Enable BitPort 2A Diagnostic Enable Bit USB Diagnostic RegisterPort 2B Diagnostic Enable Bit Port 1B Diagnostic Enable BitExternal Memory Registers Extended Page n Map Register R/W Upper Address Enable Register 0xC038 R/WUpper Address Enable Bit Extended Page n Map RegisterTimer Registers Lock Enable Bit Watchdog Timer RegisterTimeout Flag Bit WDT Enable BitUSB n Control Register Timer n RegisterGeneral USB Registers Port B D+ Status BitPort a Resistors Enable Bit Mode Select BitPort B Resistors Enable Bit EnableUSB Host Only Registers Port a SOF/EOP Enable Bit ReservedPreamble Enable Bit USB Host Only Register Register Name Address Host 1/HostArm Enable Bit Sync Enable BitHost n Address Register ISO Enable Bit Sequence Select BitStall Flag Bit Port Select BitUnderflow Flag Bit NAK Flag BitHost n PID Register W Error Flag BitSequence Status Bit Host n PID RegisterHost n Count Result Register R PID Select DefinitionPID Select Host n Count Result Register Endpoint Select BitsID Interrupt Enable Bit Host n Interrupt Enable RegisterVbus Interrupt Enable Bit Host n Device Address RegisterPort a Wake Interrupt Enable Bit SOF/EOP Interrupt Enable BitPort B Wake Interrupt Enable Bit Port B Connect Change Interrupt Enable BitPort a Wake Interrupt Flag Bit SOF/EOP Interrupt Flag BitPort B Wake Interrupt Flag Bit Port B Connect Change Interrupt Flag BitHost n Frame Register R Host n SOF/EOP Counter Register RHost n SOF/EOP Counter Register Host 1 Frame Register 0xC096 Host 2 Frame Register 0xC0B6Device n Endpoint n Control Register R/W IN/OUT Ignore Enable BitUSB Device Only Registers Device n Endpoint n Control RegisterEnable Bit Stall Enable BitNAK Interrupt Enable Bit Direction Select BitDevice n Endpoint n Count Register R/W Device n Endpoint n Count RegisterOUT Exception Flag Bit Device n Endpoint n Status Register R/WDevice n Endpoint n Status Register Exception Flag BitDevice n Endpoint n Count Result Register R/W Setup Flag BitSequence Flag Bit Device n Endpoint n Count Result RegisterDevice n Port Select Register R/W Device n Interrupt Enable Register R/WDevice n Interrupt Enable Register Port Select Bit Device n Port Select RegisterEP7 Interrupt Enable Bit SOF/EOP Timeout Interrupt Enable BitReset Interrupt Enable Bit EP6 Interrupt Enable BitDevice n Address Register EP0 Interrupt Enable BitDevice n Address Register W Device n Status Register R/WEP6 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP5 Interrupt Flag BitEP2 Interrupt Flag Bit SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits EP1 Interrupt Flag BitDevice n SOF/EOP Count Register Vbus Pull-up Enable BitOTG Control Registers OTG Control Register ReservedGpio Registers Mode Select Definition Gpio Configuration 108 Write Protect Enable BitSAS Enable Bit HSS Enable BitGpio n Output Data Register Interrupt 0 Enable BitInterrupt 0 Polarity Select Bit Reserved Gpio n Input Data RegisterIDE Registers IDE Start Address Register 0xC04A R/W Mode Select DefinitionIDE Start Address Register IDE Stop Address Register IDE Interrupt Enable BitIDE Enable Bit IDE Control RegisterIDE PIO Port Registers 0xC050 0xC06F R/W HSS RegistersHSS Registers Register Name Address Receive Interrupt Enable Bit Xoff Enable BitCTS Enable Bit HSS Control RegisterReceive Overflow Flag Bit Packet Mode Select BitTransmit Ready Bit HSS Baud Rate RegisterTransmit Gap Select Bits HSS Transmit Gap Register 0xC074 R/WHSS Transmit Gap Register HSS Data Register 0xC076 R/WHSS Receive Counter Register 0xC07A R/W HSS Receive Counter RegisterHSS Transmit Counter Register 0xC07E R/W HSS Transmit Address Register 0xC07C R/WHSS Transmit Address Register HSS Transmit Counter RegisterHPI Breakpoint Register HPI Registers Register Name Address Vbus to HPI Enable BitHPI Registers Interrupt Routing RegisterSOF/EOP2 to CPU Enable Bit ID to HPI Enable BitSOF/EOP2 to HPI Enable Bit SOF/EOP1 to HPI Enable BitSIEXmsg Register SIEXmsg Register WSIE1msg Register SIE2msg Register HPI Mailbox Register 0xC0C6 R/WVbus Flag Bit Reset2 Flag BitHPI Status Port ID Flag BitDone1 Flag Bit Reset1 Flag BitSPI Registers Mailbox Out Flag BitMaster Active Enable Bit 3Wire Enable BitPhase Select Bit Master Enable BitSPI Control Register Byte Mode BitRead Enable Bit SCK Strobe BitTransfer Interrupt Enable Bit SPI Interrupt Enable RegisterTransmit Interrupt Enable Bit Fifo Error Flag BitSPI Interrupt Clear Register Receive Interrupt Flag BitTransmit Interrupt Flag Bit Transfer Interrupt Flag BitCRC Clear Bit CRC Mode Definition CRCMode CRC Polynomial 1514CRC Enable Bit SPI CRC Value Register Receive CRC BitSPI Transmit Address Register 0xC0D8 R/W SPI Data Register 0xC0D6 R/WSPI Data Register SPI Transmit Address RegisterSPI Receive Address Register SPI Transmit Count RegisterSPI Receive Count Register Uart Registers Receive buffer full Receive buffer empty Uart Status Register 0xC0E2 RUart Status Register Uart Data Register 0xC0E4 R/WPWM Registers Register Name Address PWM Enable BitPWM Registers PWM Control RegisterPWM 1 Enable Bit PWM 3 Enable BitPWM 2 Enable Bit PWM 0 Enable BitPWM n Stop Register R/W PWM n Start Register R/WPWM n Start Register PWM n Stop RegisterPWM Cycle Count Register 0xC0FA R/W PWM Cycle Count RegisterPin Descriptions Pin DiagramPin Descriptions Name Type SCK SPI SCK D11/MOSIMosi SPI Mosi D8/MISOGPIO27/RX GPIO29/OTGIDGPIO28/TX GPIO26/CTS/PWM3Booster Power input 2.7V to Tie to Gnd for normal operationOperating Conditions DC CharacteristicsAbsolute Maximum Ratings Crystal Requirements XTALIN, XtaloutUSB Transceiver GNDReset Timing AC Timing CharacteristicsClock Timing Sram Read Cycle Parameters Description Min Typical Max Unit Sram Read Cycle15LOW Parameter Description Min Typical Max Unit Sram Write CycleSram Write Cycle Parameters HighSCL I2C Eeprom Timing-Serial IOSDA OUT HPI Host Port Interface Write Cycle Timing Read Pulse Width Chip Select Hold Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Cycle TimeHSS Byte and Block Mode Receive HSS Byte Mode TransmitHSS Block Mode Transmit IDE TimingHardware CTS/RTS Handshake Register SummaryRegister Summary HSS SOF/EOP CRC SOF/EOP2 Ordering Information Ordering Code Package Type Package DiagramsOrdering Information Pb-FreeDocument History Orig. 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