Cypress CY7C67300 manual USB Host Only Registers, Port a SOF/EOP Enable Bit Reserved

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CY7C67300

Port A SOF/EOP Enable (Bit 0)	Reserved
The Port A SOF/EOP Enable bit is only applicable in host mode.	Write all reserved bits with ’0’.
In device mode this bit must be written as ‘0’. In host mode this
bit enables or disables SOFs or EOPs for Port A. Either SOFs or
EOPs are generated depending on the LOA bit in the USB n
Control register when Port A is active.
1: Enable SOFs or EOPs
0: Disable SOFs or EOPs

USB Host Only Registers

There are twelve sets of dedicated registers for USB host only operation. Each set consists of two identical registers (unless otherwise noted), one for Host Port 1 and one for Host Port 2. These register sets are covered in this section and summarized in Table 47.

Table 47. USB Host Only Register

Register Name	Address (Host 1/Host 2)	R/W
Host n Control Register	0xC080/0xC0A0	R/W

Host n Address Register	0xC082/0xC0A2	R/W

Host n Count Register	0xC084/0xC0A4	R/W

Host n Endpoint Status Register	0xC086/0xC0A6	R

Host n PID Register	0xC086/0xC0A6	W

Host n Count Result Register	0xC088/0xC0A8	R

Host n Device Address Register	0xC088/0xC0A8	W

Host n Interrupt Enable Register	0xC08C/0xC0AC	R/W

Host n Status Register	0xC090/0xC0B0	R/W

Host n SOF/EOP Count Register	0xC092/0xC0B2	R/W

Host n SOF/EOP Counter Register	0xC094/0xC0B4	R

Host n Frame Register	0xC096/0xC0B6	R

Host n Control Register [R/W]

■Host 1 Control Register 0xC080

■Host 2 Control Register 0xC0A0

Table 48. Host n Control Register

Bit #	15	14	13	12		11	10	9	8
Field					Reserved
Read/Write	-	-	-	-		-	-	-	-
Default	0	0	0	0		0	0	0	0

Bit #	7	6	5	4	3	2	1	0
Field	Preamble	Sequence	Sync	ISO		Reserved		Arm
Field	Enable	Select	Enable	Enable				Enable
Read/Write	R/W	R/W	R/W	R/W	-	-	-	R/W
Default	0	0	0	0	0	0	0	0

Register Description

The Host n Control register allows high level USB transaction control.

Preamble Enable (Bit 7)

The Preamble Enable bit enables or disables the transmission of a preamble packet before all low-speed packets. Set this bit only when communicating with a low-speed device.

1:Enable Preamble packet

0:Disable Preamble packet

Document #: 38-08015 Rev. *J

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Contents Typical Applications EZ-Host FeaturesCY7C67300 Block Diagram Interface Descriptions IntroductionFunctional Overview USB Interface Interface Options for External Memory Bus Pins MEM PinsOTG Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number External Memory Interface External Memory Interface Pins Pin Name Pin Number External Memory Interface PinsExternal Memory Interface Block Diagrams Up to 256k x 16 External Code/Data Page ModeUart Interface General Purpose IO Interface GpioI2C Eeprom Interface Serial Peripheral InterfaceProgrammable Pulse/PWM Interface High-Speed Serial InterfaceHPI Interface Pins 3 HPI Interface Pins 3 Pin Name Pin NumberHost Port Interface IDE InterfaceIDE Interface Pins Pin Name Pin Number IDE Throughput ModeCharge Pump Interface Pins Pin Name Pin Number ActualCrystal Pins Booster PinsCrystal Pins Pin Name Pin Number Booster InterfaceBoot Configuration Interface Boot Configuration InterfaceBoot Mode Operational ModesSleep Power Savings and Reset DescriptionPower Saving Mode Description Memory Map Document # 38-08015 Rev. *JPage 15 Bank Selected 0xC018 0xC01AProcessor Control Registers RegistersBank Register Example Hex Value Binary Value Bank RegisterReserved Revision RegisterCPU Speed Definition Processor Speed Host/Device 2B Wake Enable Bit Power Control RegisterHost/Device 2A Wake Enable Bit Host/Device 1B Wake Enable BitInterrupt Enable Register Halt Enable Bit Sleep Enable BitOTG Interrupt Enable Bit SPI Interrupt Enable BitMailbox Interrupt Enable Bit HSS Interrupt Enable BitOut Mailbox Interrupt Enable Bit Uart Interrupt Enable BitPort 2B Diagnostic Enable Bit USB Diagnostic RegisterPort 2A Diagnostic Enable Bit Port 1B Diagnostic Enable BitExternal Memory Registers Upper Address Enable Bit Upper Address Enable Register 0xC038 R/WExtended Page n Map Register R/W Extended Page n Map RegisterTimer Registers Timeout Flag Bit Watchdog Timer RegisterLock Enable Bit WDT Enable BitGeneral USB Registers Timer n RegisterUSB n Control Register Port B D+ Status BitPort B Resistors Enable Bit Mode Select BitPort a Resistors Enable Bit EnablePreamble Enable Bit Port a SOF/EOP Enable Bit ReservedUSB Host Only Registers USB Host Only Register Register Name Address Host 1/HostHost n Address Register ISO Enable Bit Sync Enable BitArm Enable Bit Sequence Select BitUnderflow Flag Bit Port Select BitStall Flag Bit NAK Flag BitSequence Status Bit Error Flag BitHost n PID Register W Host n PID RegisterPID Select PID Select DefinitionHost n Count Result Register R Host n Count Result Register Endpoint Select BitsVbus Interrupt Enable Bit Host n Interrupt Enable RegisterID Interrupt Enable Bit Host n Device Address RegisterPort B Wake Interrupt Enable Bit SOF/EOP Interrupt Enable BitPort a Wake Interrupt Enable Bit Port B Connect Change Interrupt Enable BitPort B Wake Interrupt Flag Bit SOF/EOP Interrupt Flag BitPort a Wake Interrupt Flag Bit Port B Connect Change Interrupt Flag BitHost n SOF/EOP Counter Register Host n SOF/EOP Counter Register RHost n Frame Register R Host 1 Frame Register 0xC096 Host 2 Frame Register 0xC0B6USB Device Only Registers IN/OUT Ignore Enable BitDevice n Endpoint n Control Register R/W Device n Endpoint n Control RegisterNAK Interrupt Enable Bit Stall Enable BitEnable Bit Direction Select BitDevice n Endpoint n Count Register Device n Endpoint n Count Register R/WDevice n Endpoint n Status Register Device n Endpoint n Status Register R/WOUT Exception Flag Bit Exception Flag BitSequence Flag Bit Setup Flag BitDevice n Endpoint n Count Result Register R/W Device n Endpoint n Count Result RegisterDevice n Interrupt Enable Register Port Select Bit Device n Interrupt Enable Register R/WDevice n Port Select Register R/W Device n Port Select RegisterReset Interrupt Enable Bit SOF/EOP Timeout Interrupt Enable BitEP7 Interrupt Enable Bit EP6 Interrupt Enable BitDevice n Address Register W EP0 Interrupt Enable BitDevice n Address Register Device n Status Register R/WEP7 Interrupt Flag Bit Reset Interrupt Flag BitEP6 Interrupt Flag Bit EP5 Interrupt Flag BitSOF/EOP Timeout Interrupt Counter Bits SOF/EOP Timeout Flag BitEP2 Interrupt Flag Bit EP1 Interrupt Flag BitOTG Control Registers Vbus Pull-up Enable BitDevice n SOF/EOP Count Register OTG Control Register ReservedGpio Registers SAS Enable Bit Write Protect Enable BitMode Select Definition Gpio Configuration 108 HSS Enable BitInterrupt 0 Polarity Select Bit Reserved Interrupt 0 Enable BitGpio n Output Data Register Gpio n Input Data RegisterIDE Registers IDE Start Address Register Mode Select DefinitionIDE Start Address Register 0xC04A R/W IDE Enable Bit IDE Interrupt Enable BitIDE Stop Address Register IDE Control RegisterHSS Registers Register Name Address HSS RegistersIDE PIO Port Registers 0xC050 0xC06F R/W CTS Enable Bit Xoff Enable BitReceive Interrupt Enable Bit HSS Control RegisterTransmit Ready Bit Packet Mode Select BitReceive Overflow Flag Bit HSS Baud Rate RegisterHSS Transmit Gap Register HSS Transmit Gap Register 0xC074 R/WTransmit Gap Select Bits HSS Data Register 0xC076 R/WHSS Receive Counter Register HSS Receive Counter Register 0xC07A R/WHSS Transmit Address Register HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W HSS Transmit Counter RegisterHPI Registers Vbus to HPI Enable BitHPI Breakpoint Register HPI Registers Register Name Address Interrupt Routing RegisterSOF/EOP2 to HPI Enable Bit ID to HPI Enable BitSOF/EOP2 to CPU Enable Bit SOF/EOP1 to HPI Enable BitSIE1msg Register SIE2msg Register SIEXmsg Register WSIEXmsg Register HPI Mailbox Register 0xC0C6 R/WHPI Status Port Reset2 Flag BitVbus Flag Bit ID Flag BitSPI Registers Reset1 Flag BitDone1 Flag Bit Mailbox Out Flag BitPhase Select Bit 3Wire Enable BitMaster Active Enable Bit Master Enable BitRead Enable Bit Byte Mode BitSPI Control Register SCK Strobe BitTransmit Interrupt Enable Bit SPI Interrupt Enable RegisterTransfer Interrupt Enable Bit Fifo Error Flag BitTransmit Interrupt Flag Bit Receive Interrupt Flag BitSPI Interrupt Clear Register Transfer Interrupt Flag BitCRC Enable Bit CRC Mode Definition CRCMode CRC Polynomial 1514CRC Clear Bit SPI CRC Value Register Receive CRC BitSPI Data Register SPI Data Register 0xC0D6 R/WSPI Transmit Address Register 0xC0D8 R/W SPI Transmit Address RegisterSPI Receive Count Register SPI Transmit Count RegisterSPI Receive Address Register Uart Registers Uart Status Register Uart Status Register 0xC0E2 RReceive buffer full Receive buffer empty Uart Data Register 0xC0E4 R/WPWM Registers PWM Enable BitPWM Registers Register Name Address PWM Control RegisterPWM 2 Enable Bit PWM 3 Enable BitPWM 1 Enable Bit PWM 0 Enable BitPWM n Start Register PWM n Start Register R/WPWM n Stop Register R/W PWM n Stop RegisterPWM Cycle Count Register PWM Cycle Count Register 0xC0FA R/WPin Descriptions Name Type Pin DiagramPin Descriptions Mosi SPI Mosi D11/MOSISCK SPI SCK D8/MISOGPIO28/TX GPIO29/OTGIDGPIO27/RX GPIO26/CTS/PWM3Tie to Gnd for normal operation Booster Power input 2.7V toAbsolute Maximum Ratings DC CharacteristicsOperating Conditions Crystal Requirements XTALIN, XtaloutGND USB TransceiverClock Timing AC Timing CharacteristicsReset Timing LOW Sram Read Cycle15Sram Read Cycle Parameters Description Min Typical Max Unit Sram Write Cycle Parameters Sram Write CycleParameter Description Min Typical Max Unit HighSDA OUT I2C Eeprom Timing-Serial IOSCL HPI Host Port Interface Write Cycle Timing HPI Host Port Interface Read Cycle Timing Chip Select Hold Data Access Time, from HPInRD fallingRead Pulse Width Read Cycle TimeHSS Block Mode Transmit HSS Byte Mode TransmitHSS Byte and Block Mode Receive IDE TimingRegister Summary Register SummaryHardware CTS/RTS Handshake HSS SOF/EOP CRC SOF/EOP2 Ordering Information Package DiagramsOrdering Information Ordering Code Package Type Pb-FreeOrig. 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