Cypress CY7C67300 Boost 3V OK Bit, Sleep Enable Bit, Interrupt Enable Register Halt Enable Bit

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CY7C67300

Boost 3V OK (Bit 2)

The Boost 3V OK bit is a read only bit that returns the status of the OTG Boost circuit.

1:Boost circuit not ok and internal voltage rails are below 3.0V

0:Boost circuit ok and internal voltage rails are at or above 3.0V

Sleep Enable (Bit 1)

Setting this bit to ‘1’ immediately initiates SLEEP mode. While in SLEEP mode, the entire chip is paused, achieving the lowest standby power state. All operations are paused, the internal clock is stopped, the booster circuit and OTG VBUS charge pump are all powered down, and the USB transceivers are powered down. All counters and timers are paused but retain their values; enabled PWM outputs freeze in their current states. SLEEP mode exits by any activity selected in this register. When SLEEP mode ends, instruction execution resumes within 0.5 ms.

1:Enable Sleep mode

0:No function

Interrupt Enable Register [0xC00E] [R/W]

Table 29. Interrupt Enable Register

Halt Enable (Bit 0)

Setting this bit to ‘1’ immediately initiates HALT mode. While in HALT mode, only the CPU is stopped. The internal clock still runs and all peripherals still operate, including the USB engines. The power saving using HALT in most cases is minimal, but in appli- cations that are very CPU intensive the incremental savings may provide some benefit.

The HALT state is exited when any enabled interrupt is triggered. Upon exiting the HALT state, one or two instructions immediately following the HALT instruction may be executed before the waking interrupt is serviced (you may want to follow the HALT instruction with two NOPs).

1:Enable Halt mode

0:No function

Reserved

Write all reserved bits with ’0’.

Bit #

15

14

13

12

11

10

9

8

 

 

Reserved

 

OTG

SPI

Reserved

Host/Device 2

Host/Device 1

Field

 

 

 

Interrupt

Interrupt

 

Interrupt

Interrupt

 

 

 

Enable

Enable

 

Enable

Enable

Read/Write

-

-

-

R/W

R/W

-

R/W

R/W

Default

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

Bit #

7

6

5

4

3

2

1

0

 

HSS

In Mailbox

Out Mailbox

Reserved

UART

GPIO

Timer 1

Timer 0

Field

Interrupt

Interrupt

Interrupt

 

Interrupt

Interrupt

Interrupt

Interrupt

Enable

Enable

Enable

 

Enable

Enable

Enable

Enable

Read/Write

R/W

R/W

R/W

-

R/W

R/W

R/W

R/W

Default

0

0

0

1

0

0

0

0

 

 

 

 

 

 

 

 

 

Register Description

The Interrupt Enable register allows control of the hardware interrupt vectors.

OTG Interrupt Enable (Bit 12)

The OTG Interrupt Enable bit enables or disables the OTG ID/OTG4.4V Valid hardware interrupt.

1:Enable OTG interrupt

0:Disable OTG interrupt

SPI Interrupt Enable (Bit 11)

The SPI Interrupt Enable bit enables or disables the following three SPI hardware interrupts: SPI TX, SPI RX, and SPI DMA Block Done.

1:Enable SPI interrupt

0:Disable SPI interrupt

Host/Device 2 Interrupt Enable (Bit 9)

The Host/Device 2 Interrupt Enable bit enables or disables all of the following Host/Device 2 hardware interrupts: Host 2 USB Done, Host 2 USB SOF/EOP, Host 2 Wakeup/Insert/Remove, Device 2 Reset, Device 2 SOF/EOP or WakeUp from USB, Device 2 Endpoint n.

1:Enable Host 2 and Device 2 interrupt

0:Disable Host 2 and Device 2 interrupt

Host/Device 1 Interrupt Enable (Bit 8)

The Host/Device 1 Interrupt Enable bit enables or disables all of the following Host/Device 1 hardware interrupts: Host 1 USB Done, Host 1 USB SOF/EOP, Host 1 Wakeup/Insert/Remove, Device 1 Reset, Device 1 SOF/EOP or WakeUp from USB, Device 1Endpoint n.

1:Enable Host 1 and Device 1 interrupt

0:Disable Host 1 and Device 1 interrupt

Document #: 38-08015 Rev. *J

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Contents Typical Applications EZ-Host FeaturesCY7C67300 Block Diagram Interface Descriptions IntroductionFunctional Overview Interface Options for External Memory Bus Pins MEM Pins USB InterfaceOTG Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number External Memory Interface External Memory Interface Pins External Memory Interface Pins Pin Name Pin NumberExternal Memory Interface Block Diagrams Up to 256k x 16 External Code/Data Page ModeGeneral Purpose IO Interface Gpio Uart InterfaceI2C Eeprom Interface Serial Peripheral InterfaceHigh-Speed Serial Interface Programmable Pulse/PWM InterfaceHPI Interface Pins 3 Pin Name Pin Number HPI Interface Pins 3Host Port Interface IDE InterfaceIDE Throughput Mode IDE Interface Pins Pin Name Pin NumberCharge Pump Interface Pins Pin Name Pin Number ActualBooster Pins Crystal PinsCrystal Pins Pin Name Pin Number Booster InterfaceBoot Configuration Interface Boot Configuration InterfaceBoot Mode Operational ModesSleep Power Savings and Reset DescriptionPower Saving Mode Description Memory Map Bank Selected 0xC018 0xC01A Document # 38-08015 Rev. *JPage 15Registers Processor Control RegistersBank Register Bank Register Example Hex Value Binary ValueReserved Revision RegisterCPU Speed Definition Processor Speed Power Control Register Host/Device 2B Wake Enable BitHost/Device 2A Wake Enable Bit Host/Device 1B Wake Enable BitSleep Enable Bit Interrupt Enable Register Halt Enable BitOTG Interrupt Enable Bit SPI Interrupt Enable BitHSS Interrupt Enable Bit Mailbox Interrupt Enable BitOut Mailbox Interrupt Enable Bit Uart Interrupt Enable BitUSB Diagnostic Register Port 2B Diagnostic Enable BitPort 2A Diagnostic Enable Bit Port 1B Diagnostic Enable BitExternal Memory Registers Upper Address Enable Register 0xC038 R/W Upper Address Enable BitExtended Page n Map Register R/W Extended Page n Map RegisterTimer Registers Watchdog Timer Register Timeout Flag BitLock Enable Bit WDT Enable BitTimer n Register General USB RegistersUSB n Control Register Port B D+ Status BitMode Select Bit Port B Resistors Enable BitPort a Resistors Enable Bit EnablePort a SOF/EOP Enable Bit Reserved Preamble Enable BitUSB Host Only Registers USB Host Only Register Register Name Address Host 1/HostSync Enable Bit Host n Address Register ISO Enable BitArm Enable Bit Sequence Select BitPort Select Bit Underflow Flag BitStall Flag Bit NAK Flag BitError Flag Bit Sequence Status BitHost n PID Register W Host n PID RegisterPID Select Definition PID SelectHost n Count Result Register R Host n Count Result Register Endpoint Select BitsHost n Interrupt Enable Register Vbus Interrupt Enable BitID Interrupt Enable Bit Host n Device Address RegisterSOF/EOP Interrupt Enable Bit Port B Wake Interrupt Enable BitPort a Wake Interrupt Enable Bit Port B Connect Change Interrupt Enable BitSOF/EOP Interrupt Flag Bit Port B Wake Interrupt Flag BitPort a Wake Interrupt Flag Bit Port B Connect Change Interrupt Flag BitHost n SOF/EOP Counter Register R Host n SOF/EOP Counter RegisterHost n Frame Register R Host 1 Frame Register 0xC096 Host 2 Frame Register 0xC0B6IN/OUT Ignore Enable Bit USB Device Only RegistersDevice n Endpoint n Control Register R/W Device n Endpoint n Control RegisterStall Enable Bit NAK Interrupt Enable BitEnable Bit Direction Select BitDevice n Endpoint n Count Register R/W Device n Endpoint n Count RegisterDevice n Endpoint n Status Register R/W Device n Endpoint n Status RegisterOUT Exception Flag Bit Exception Flag BitSetup Flag Bit Sequence Flag BitDevice n Endpoint n Count Result Register R/W Device n Endpoint n Count Result RegisterDevice n Interrupt Enable Register R/W Device n Interrupt Enable Register Port Select BitDevice n Port Select Register R/W Device n Port Select RegisterSOF/EOP Timeout Interrupt Enable Bit Reset Interrupt Enable BitEP7 Interrupt Enable Bit EP6 Interrupt Enable BitEP0 Interrupt Enable Bit Device n Address Register WDevice n Address Register Device n Status Register R/WReset Interrupt Flag Bit EP7 Interrupt Flag BitEP6 Interrupt Flag Bit EP5 Interrupt Flag BitSOF/EOP Timeout Flag Bit SOF/EOP Timeout Interrupt Counter BitsEP2 Interrupt Flag Bit EP1 Interrupt Flag BitVbus Pull-up Enable Bit OTG Control RegistersDevice n SOF/EOP Count Register OTG Control Register ReservedGpio Registers Write Protect Enable Bit SAS Enable BitMode Select Definition Gpio Configuration 108 HSS Enable BitInterrupt 0 Enable Bit Interrupt 0 Polarity Select Bit ReservedGpio n Output Data Register Gpio n Input Data RegisterIDE Registers IDE Start Address Register Mode Select DefinitionIDE Start Address Register 0xC04A R/W IDE Interrupt Enable Bit IDE Enable BitIDE Stop Address Register IDE Control RegisterHSS Registers Register Name Address HSS RegistersIDE PIO Port Registers 0xC050 0xC06F R/W Xoff Enable Bit CTS Enable BitReceive Interrupt Enable Bit HSS Control RegisterPacket Mode Select Bit Transmit Ready BitReceive Overflow Flag Bit HSS Baud Rate RegisterHSS Transmit Gap Register 0xC074 R/W HSS Transmit Gap RegisterTransmit Gap Select Bits HSS Data Register 0xC076 R/WHSS Receive Counter Register 0xC07A R/W HSS Receive Counter RegisterHSS Transmit Address Register 0xC07C R/W HSS Transmit Address RegisterHSS Transmit Counter Register 0xC07E R/W HSS Transmit Counter RegisterVbus to HPI Enable Bit HPI RegistersHPI Breakpoint Register HPI Registers Register Name Address Interrupt Routing RegisterID to HPI Enable Bit SOF/EOP2 to HPI Enable BitSOF/EOP2 to CPU Enable Bit SOF/EOP1 to HPI Enable BitSIEXmsg Register W SIE1msg Register SIE2msg RegisterSIEXmsg Register HPI Mailbox Register 0xC0C6 R/WReset2 Flag Bit HPI Status PortVbus Flag Bit ID Flag BitReset1 Flag Bit SPI RegistersDone1 Flag Bit Mailbox Out Flag Bit3Wire Enable Bit Phase Select BitMaster Active Enable Bit Master Enable BitByte Mode Bit Read Enable BitSPI Control Register SCK Strobe BitSPI Interrupt Enable Register Transmit Interrupt Enable BitTransfer Interrupt Enable Bit Fifo Error Flag BitReceive Interrupt Flag Bit Transmit Interrupt Flag BitSPI Interrupt Clear Register Transfer Interrupt Flag BitCRC Mode Definition CRCMode CRC Polynomial 1514 CRC Enable BitCRC Clear Bit SPI CRC Value Register Receive CRC BitSPI Data Register 0xC0D6 R/W SPI Data RegisterSPI Transmit Address Register 0xC0D8 R/W SPI Transmit Address RegisterSPI Receive Count Register SPI Transmit Count RegisterSPI Receive Address Register Uart Registers Uart Status Register 0xC0E2 R Uart Status RegisterReceive buffer full Receive buffer empty Uart Data Register 0xC0E4 R/WPWM Enable Bit PWM RegistersPWM Registers Register Name Address PWM Control RegisterPWM 3 Enable Bit PWM 2 Enable BitPWM 1 Enable Bit PWM 0 Enable BitPWM n Start Register R/W PWM n Start RegisterPWM n Stop Register R/W PWM n Stop RegisterPWM Cycle Count Register 0xC0FA R/W PWM Cycle Count RegisterPin Descriptions Name Type Pin DiagramPin Descriptions D11/MOSI Mosi SPI MosiSCK SPI SCK D8/MISOGPIO29/OTGID GPIO28/TXGPIO27/RX GPIO26/CTS/PWM3Booster Power input 2.7V to Tie to Gnd for normal operationDC Characteristics Absolute Maximum RatingsOperating Conditions Crystal Requirements XTALIN, XtaloutUSB Transceiver GNDClock Timing AC Timing CharacteristicsReset Timing LOW Sram Read Cycle15Sram Read Cycle Parameters Description Min Typical Max Unit Sram Write Cycle Sram Write Cycle ParametersParameter Description Min Typical Max Unit HighSDA OUT I2C Eeprom Timing-Serial IOSCL HPI Host Port Interface Write Cycle Timing Chip Select Hold Data Access Time, from HPInRD falling HPI Host Port Interface Read Cycle TimingRead Pulse Width Read Cycle TimeHSS Byte Mode Transmit HSS Block Mode TransmitHSS Byte and Block Mode Receive IDE TimingRegister Summary Register SummaryHardware CTS/RTS Handshake HSS SOF/EOP CRC SOF/EOP2 Package Diagrams Ordering InformationOrdering Information Ordering Code Package Type Pb-FreeDocument History Orig. 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