Cypress CY7C67300 Host Port Interface, IDE Interface, HPI Interface Pins 3 Pin Name Pin Number

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CY7C67300

Host Port Interface

EZ-Host has an HPI interface. The HPI interface provides DMA access to the EZ-Host internal memory by an external host, plus a bidirectional mailbox register for supporting high level commu- nication protocols. This port is designed to be the primary high-speed connection to a host processor. Complete control of EZ-Host can be accomplished through this interface via an extensible API and communication protocol. Other than the hardware communication protocols, a host processor has identical control over EZ-Host whether connecting to the HPI or HSS port. The HPI interface is exposed through GPIO pins.

HPI Features

■16-bit data bus interface

■16 MB/s throughput

■Auto-increment of address pointer for fast block mode transfers

■Direct memory access (DMA) to internal memory

■Bidirectional Mailbox register

■Byte swapping

■Complete access to internal memory

■Complete control of SIEs through HPI

■Dedicated HPI status register

HPI Pins

Table 12. HPI Interface Pins [3, 4]

Pin Name	Pin Number
INT	46

nRD	47

nWR	48

nCS	49

A1	50

A0	52

D15	56

D14	57

D13	58

D12	59

Table 12. HPI Interface Pins (continued)[3, 4]

D11	60

D10	61

D9	65

D8	66

D7	86

D6	87

D5	89

D4	90

D3	91

D2	92

D1	93

D0	94

The two HPI address pins are used to address one of four possible HPI port registers as shown in Table 13.

Table 13. HPI Addressing

HPI A[1:0]	A1	A0
HPI Data	0	0

HPI Mailbox	0	1

HPI Address	1	0

HPI Status	1	1

IDE Interface

EZ-Host has an IDE interface. The IDE interface supports PIO mode 0-4 as specified in the Information Technology-AT Attachment–4 with Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18. There is no need for firmware to use programmable wait states. The CPU read/write cycle is automatically extended as needed for direct CPU to IDE read/write accesses.

The EZ-Host IDE interface also has a BLOCK transfer mode that allows EZ-Host to read/write large blocks of data to/from the IDE data register and move it to/from the EZ-Host on-chip memory directly without intervention of the CPU. The IDE interface is exposed through GPIO pins. Table 14 on page 10 lists the achieved throughput for maximum block mode data transfer rate (with IDE_IORDY true) for the various IDE PIO modes.

Notes

3.HPI_INT is for the Outgoing Mailbox interrupt.

4.HPI strobes are negative logic sampled on rising edge.

Document #: 38-08015 Rev. *J

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Contents EZ-Host Features CY7C67300 Block DiagramTypical Applications Introduction Functional OverviewInterface Descriptions USB Interface Interface Options for External Memory Bus Pins MEM PinsUSB Interface Pins Pin Name Pin Number OTG Interface Pins Pin Name Pin NumberOTG Interface External Memory Interface External Memory Interface Pins Pin Name Pin Number External Memory Interface PinsExternal Memory Interface Block Diagrams Up to 256k x 16 External Code/Data Page ModeUart Interface General Purpose IO Interface GpioI2C Eeprom Interface Serial Peripheral InterfaceProgrammable Pulse/PWM Interface High-Speed Serial InterfaceHPI Interface Pins 3 HPI Interface Pins 3 Pin Name Pin NumberHost Port Interface IDE InterfaceIDE Interface Pins Pin Name Pin Number IDE Throughput ModeCharge Pump Interface Pins Pin Name Pin Number ActualCrystal Pins Booster PinsCrystal Pins Pin Name Pin Number Booster InterfaceBoot Configuration Interface Boot Configuration InterfaceBoot Mode Operational ModesPower Savings and Reset Description Power Saving Mode DescriptionSleep Memory Map Document # 38-08015 Rev. *JPage 15 Bank Selected 0xC018 0xC01AProcessor Control Registers RegistersBank Register Example Hex Value Binary Value Bank RegisterReserved Revision RegisterCPU Speed Definition Processor Speed Host/Device 2B Wake Enable Bit Power Control RegisterHost/Device 2A Wake Enable Bit Host/Device 1B Wake Enable BitInterrupt Enable Register Halt Enable Bit Sleep Enable BitOTG Interrupt Enable Bit SPI Interrupt Enable BitMailbox Interrupt Enable Bit HSS Interrupt Enable BitOut Mailbox Interrupt Enable Bit Uart Interrupt Enable BitPort 2B Diagnostic Enable Bit USB Diagnostic RegisterPort 2A Diagnostic Enable Bit Port 1B Diagnostic Enable BitExternal Memory Registers Upper Address Enable Bit Upper Address Enable Register 0xC038 R/WExtended Page n Map Register R/W Extended Page n Map RegisterTimer Registers Timeout Flag Bit Watchdog Timer RegisterLock Enable Bit WDT Enable BitGeneral USB Registers Timer n RegisterUSB n Control Register Port B D+ Status BitPort B Resistors Enable Bit Mode Select BitPort a Resistors Enable Bit EnablePreamble Enable Bit Port a SOF/EOP Enable Bit ReservedUSB Host Only Registers USB Host Only Register Register Name Address Host 1/HostHost n Address Register ISO Enable Bit Sync Enable BitArm Enable Bit Sequence Select BitUnderflow Flag Bit Port Select BitStall Flag Bit NAK Flag BitSequence Status Bit Error Flag BitHost n PID Register W Host n PID RegisterPID Select PID Select DefinitionHost n Count Result Register R Host n Count Result Register Endpoint Select BitsVbus Interrupt Enable Bit Host n Interrupt Enable RegisterID Interrupt Enable Bit Host n Device Address RegisterPort B Wake Interrupt Enable Bit SOF/EOP Interrupt Enable BitPort a Wake Interrupt Enable Bit Port B Connect Change Interrupt Enable BitPort B Wake Interrupt Flag Bit SOF/EOP Interrupt Flag BitPort a Wake Interrupt Flag Bit Port B Connect Change Interrupt Flag BitHost n SOF/EOP Counter Register Host n SOF/EOP Counter Register RHost n Frame Register R Host 1 Frame Register 0xC096 Host 2 Frame Register 0xC0B6USB Device Only Registers IN/OUT Ignore Enable BitDevice n Endpoint n Control Register R/W Device n Endpoint n Control RegisterNAK Interrupt Enable Bit Stall Enable BitEnable Bit Direction Select BitDevice n Endpoint n Count Register Device n Endpoint n Count Register R/WDevice n Endpoint n Status Register Device n Endpoint n Status Register R/WOUT Exception Flag Bit Exception Flag BitSequence Flag Bit Setup Flag BitDevice n Endpoint n Count Result Register R/W Device n Endpoint n Count Result RegisterDevice n Interrupt Enable Register Port Select Bit Device n Interrupt Enable Register R/WDevice n Port Select Register R/W Device n Port Select RegisterReset Interrupt Enable Bit SOF/EOP Timeout Interrupt Enable BitEP7 Interrupt Enable Bit EP6 Interrupt Enable BitDevice n Address Register W EP0 Interrupt Enable BitDevice n Address Register Device n Status Register R/WEP7 Interrupt Flag Bit Reset Interrupt Flag BitEP6 Interrupt Flag Bit EP5 Interrupt Flag BitSOF/EOP Timeout Interrupt Counter Bits SOF/EOP Timeout Flag BitEP2 Interrupt Flag Bit EP1 Interrupt Flag BitOTG Control Registers Vbus Pull-up Enable BitDevice n SOF/EOP Count Register OTG Control Register ReservedGpio Registers SAS Enable Bit Write Protect Enable BitMode Select Definition Gpio Configuration 108 HSS Enable BitInterrupt 0 Polarity Select Bit Reserved Interrupt 0 Enable BitGpio n Output Data Register Gpio n Input Data RegisterIDE Registers Mode Select Definition IDE Start Address Register 0xC04A R/WIDE Start Address Register IDE Enable Bit IDE Interrupt Enable BitIDE Stop Address Register IDE Control RegisterHSS Registers IDE PIO Port Registers 0xC050 0xC06F R/WHSS Registers Register Name Address CTS Enable Bit Xoff Enable BitReceive Interrupt Enable Bit HSS Control RegisterTransmit Ready Bit Packet Mode Select BitReceive Overflow Flag Bit HSS Baud Rate RegisterHSS Transmit Gap Register HSS Transmit Gap Register 0xC074 R/WTransmit Gap Select Bits HSS Data Register 0xC076 R/WHSS Receive Counter Register HSS Receive Counter Register 0xC07A R/WHSS Transmit Address Register HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W HSS Transmit Counter RegisterHPI Registers Vbus to HPI Enable BitHPI Breakpoint Register HPI Registers Register Name Address Interrupt Routing RegisterSOF/EOP2 to HPI Enable Bit ID to HPI Enable BitSOF/EOP2 to CPU Enable Bit SOF/EOP1 to HPI Enable BitSIE1msg Register SIE2msg Register SIEXmsg Register WSIEXmsg Register HPI Mailbox Register 0xC0C6 R/WHPI Status Port Reset2 Flag BitVbus Flag Bit ID Flag BitSPI Registers Reset1 Flag BitDone1 Flag Bit Mailbox Out Flag BitPhase Select Bit 3Wire Enable BitMaster Active Enable Bit Master Enable BitRead Enable Bit Byte Mode BitSPI Control Register SCK Strobe BitTransmit Interrupt Enable Bit SPI Interrupt Enable RegisterTransfer Interrupt Enable Bit Fifo Error Flag BitTransmit Interrupt Flag Bit Receive Interrupt Flag BitSPI Interrupt Clear Register Transfer Interrupt Flag BitCRC Enable Bit CRC Mode Definition CRCMode CRC Polynomial 1514CRC Clear Bit SPI CRC Value Register Receive CRC BitSPI Data Register SPI Data Register 0xC0D6 R/WSPI Transmit Address Register 0xC0D8 R/W SPI Transmit Address RegisterSPI Transmit Count Register SPI Receive Address RegisterSPI Receive Count Register Uart Registers Uart Status Register Uart Status Register 0xC0E2 RReceive buffer full Receive buffer empty Uart Data Register 0xC0E4 R/WPWM Registers PWM Enable BitPWM Registers Register Name Address PWM Control RegisterPWM 2 Enable Bit PWM 3 Enable BitPWM 1 Enable Bit PWM 0 Enable BitPWM n Start Register PWM n Start Register R/WPWM n Stop Register R/W PWM n Stop RegisterPWM Cycle Count Register PWM Cycle Count Register 0xC0FA R/WPin Diagram Pin DescriptionsPin Descriptions Name Type Mosi SPI Mosi D11/MOSISCK SPI SCK D8/MISOGPIO28/TX GPIO29/OTGIDGPIO27/RX GPIO26/CTS/PWM3Tie to Gnd for normal operation Booster Power input 2.7V toAbsolute Maximum Ratings DC CharacteristicsOperating Conditions Crystal Requirements XTALIN, XtaloutGND USB TransceiverAC Timing Characteristics Reset TimingClock Timing Sram Read Cycle15 Sram Read Cycle Parameters Description Min Typical Max UnitLOW Sram Write Cycle Parameters Sram Write CycleParameter Description Min Typical Max Unit HighI2C Eeprom Timing-Serial IO SCLSDA OUT HPI Host Port Interface Write Cycle Timing HPI Host Port Interface Read Cycle Timing Chip Select Hold Data Access Time, from HPInRD fallingRead Pulse Width Read Cycle TimeHSS Block Mode Transmit HSS Byte Mode TransmitHSS Byte and Block Mode Receive IDE TimingRegister Summary Hardware CTS/RTS HandshakeRegister Summary HSS SOF/EOP CRC SOF/EOP2 Ordering Information Package DiagramsOrdering Information Ordering Code Package Type Pb-FreeOrig. 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