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Watchdog Timer Register [0xC00C] [R/W] |
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Table 40. Watchdog Timer Register |
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Bit # | 15 | 14 | 13 | 12 |
| 11 | 10 | 9 |
| 8 |
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Field |
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| Reserved... |
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Read/Write | R/W |
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| R/W | R/W | R/W |
| R/W | R/W | R/W |
| R/W |
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Default | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 |
| 0 |
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Bit # | 7 | 6 | 5 | 4 |
| 3 | 2 | 1 |
| 0 |
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Field | ...Reserved | Timeout |
| Period | Lock | WDT |
| Reset |
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| Flag |
| Select | Enable | Enable |
| Strobe |
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Read/Write | R/W |
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| R/W | R/W | R/W |
| R/W | R/W | R/W |
| W |
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Default | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 |
| 0 |
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Register Description
The Watchdog Timer register provides status and control over the Watchdog timer. The Watchdog timer can also interrupt the processor.
Timeout Flag (Bit 5)
The Timeout Flag bit indicates if the Watchdog timer expired. The processor can read this bit after exiting a reset to determine if a Watchdog timeout occurred. This bit is cleared on the next external hardware reset.
1:Watchdog timer expired.
0:Watchdog timer did not expire.
Period Select (Bits [4:3])
The Period Select field is defined in Table 41. If this time expires before the Reset Strobe bit is set, the internal processor is reset.
Table 41. Period Select Definition
Period Select[4:3] | WDT Period Value |
00 | 1.4 ms |
01 | 5.5 ms |
10 | 22.0 ms |
11 | 66.0 ms |
Lock Enable (Bit 2)
The Lock Enable bit does not allow any writes to this register until a reset. In doing so the Watchdog timer can be set up and enabled permanently so that it can only be cleared on reset (the WDT Enable bit is ignored).
1:Watchdog timer permanently set
0:Watchdog timer not permanently set
WDT Enable (Bit 1)
The WDT Enable bit enables or disables the Watchdog timer.
1:Enable Watchdog timer operation
0:Disable Watchdog timer operation
Reset Strobe (Bit 0)
The Reset Strobe is a
1:Reset Count
Reserved
Write all reserved bits with ’0’.
Document #: | Page 26 of 99 |
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