Cypress CY7C68034, CY7C68033 manual ECC Generation5, Autopointer Access, I2C Controller

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CY7C68033/CY7C68034

the default NAND firmware image implements an 8-bit data bus and up to 8 chip enable pins on the GPIF ports, it is recom- mended that designs based upon the default firmware image use an 8-bit data bus as well.

Each GPIF vector defines the state of the control outputs, and determines what state a ready input (or multiple inputs) must be before proceeding. The GPIF vector can be programmed to advance a FIFO to the next data value, advance an address, etc. A sequence of the GPIF vectors make up a single waveform that will be executed to perform the desired data move between the NX2LP-Flex and the external device.

Three Control OUT Signals

The NX2LP-Flex exposes three control signals, CTL[2:0]. CTLx waveform edges can be programmed to make transi- tions as fast as once per clock (20.8 ns using a 48-MHz clock).

Two Ready IN Signals

The 8051 programs the GPIF unit to test the RDY pins for GPIF branching. The 56-pin package brings out two signals, RDY[1:0].

Long Transfer Mode

In GPIF Master mode, the 8051 appropriately sets GPIF trans- action count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or GPIFTCB0) for unattended transfers of up to 232 transactions. The GPIF automatically throttles data flow to prevent under- or over-flow until the full number of requested transactions complete. The GPIF decrements the value in these registers to represent the current status of the transaction.

ECC Generation[5]

The NX2LP-Flex can calculate ECCs (Error-Correcting Codes) on data that passes across its GPIF or Slave FIFO interfaces. There are two ECC configurations:

•Two ECCs, each calculated over 256 bytes (SmartMedia Standard)

•One ECC calculated over 512 bytes.

The two ECC configurations described below are selected by the ECCM bit. The ECC can correct any one-bit error or detect any two-bit error.

ECCM = 0

Two 3-byte ECCs, each calculated over a 256-byte block of data. This configuration conforms to the SmartMedia Standard and is used by both the NAND boot logic and default NAND firmware image.

When any value is written to ECCRESET and data is then passed across the GPIF or Slave FIFO interface, the ECC for the first 256 bytes of data will be calculated and stored in ECC1. The ECC for the next 256 bytes of data will be stored in ECC2. After the second ECC is calculated, the values in the ECCx registers will not change until ECCRESET is written again, even if more data is subsequently passed across the interface.

ECCM = 1

One 3-byte ECC calculated over a 512-byte block of data.

When any value is written to ECCRESET and data is then passed across the GPIF or Slave FIFO interface, the ECC for the first 512 bytes of data will be calculated and stored in ECC1; ECC2 is unused. After the ECC is calculated, the value in ECC1 will not change until ECCRESET is written again, even if more data is subsequently passed across the interface

Autopointer Access

NX2LP-Flex provides two identical autopointers. They are similar to the internal 8051 data pointers, but with an additional feature: they can optionally increment after every memory access. Also, the autopointers can point to any NX2LP-Flex register or endpoint buffer space.

I2C Controller

NX2LP has one I2C port that the 8051, once running uses to control external I2C devices. The I2C port operates in master mode only. The I2C post is disabled at startup and only available for use after the initial NAND access.

I2C Port Pins

The I2C pins SCL and SDA must have external 2.2-kΩpull-up resistors even if no EEPROM is connected to the NX2LP.

I2C Interface General-Purpose Access

The 8051 can control peripherals connected to the I2C bus using the I2CTL and I2DATA registers. NX2LP provides I2C master control only and is never an I2C slave.

Note

5. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.

Document #: 001-04247 Rev. *D

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Contents CY7C68033 Only Silicon Features CY7C68033/CY7C68034 Silicon FeaturesBlock Diagram CY7C68034 Only Silicon FeaturesApplications Default Nand Firmware FeaturesOverview Special Function Registers USB Signaling SpeedFunctional Overview Clock FrequencyOEB DPL1 OEC DPH1 OED DPS OEE IOA IOB IOC IODPSW ACC Exif INT2CLR IOE SBUF1 Mpage INT4CLR OEAReNumeration Default Silicon ID Values Default VID/PID/DIDBus-powered Applications Default Silicon ID ValuesFIFO/GPIF Interrupt INT4 INT2 USB InterruptsUSB Interrupt Table for INT2 Priority INT2VEC Value SourceReset Pin Reset and WakeupRegister Addresses Reset Timing Values ConditionProgram/Data RAM Endpoint RAM Default Full-Speed Alternate Settings2Gpif Default High-Speed Alternate Settings2External Fifo Interface I2C Controller Autopointer AccessECC Generation5 Pin Assignments Feature programmable polarityCY7C68033/CY7C68034 Type NX2LP-Flex Pin Descriptions 56 QFN Default PinPin Default Description Name NandPort a Port D Port BGround Power and GroundNX2LP-Flex Register Summary Register SummaryRegister can only be reset, it cannot be set Nakirq EP0CS E6CD Flowstbperiod SEL Operating Conditions Absolute Maximum RatingsUSB Transceiver DC CharacteristicsAC Electrical Characteristics Slave Fifo Asynchronous Write Slave Fifo Asynchronous ReadSlave Fifo Address to Flags/Data Slave Fifo Output EnableSlave Fifo Asynchronous Packet End Strobe Slave Fifo Asynchronous Address FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeRD/WR/PKTEND to FIFOADR10 Hold Time Sequence Diagram Sequence Diagram of a Single and Burst Asynchronous ReadSlave Fifo Asynchronous Write Sequence and Timing Diagram13 Sequence Diagram of a Single and Burst Asynchronous WriteOrdering Information Package DiagramQuad Flat Package No Leads QFN Package Design Notes PCB Layout Recommendations16Plot of the Solder Mask White Area REV ECN no Issue Date Orig. Description of ChangeDocument History
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