Cypress CY7C68033, CY7C68034 manual E6CD Flowstbperiod

Page 22

CY7C68033/CY7C68034

Table 9. NX2LP-Flex Register Summary (continued)

Hex

Size

Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

E6CD

1

FLOWSTBPERIOD

Master-Strobe Half-Period

D7

D6

D5

D4

D3

D2

D1

D0

00000010

RW

E6CE

1

GPIFTCB3[7]

GPIF Transaction Count

TC31

TC30

TC29

TC28

TC27

TC26

TC25

TC24

00000000

RW

Byte 3

E6CF

1

GPIFTCB2[7]

GPIF Transaction Count

TC23

TC22

TC21

TC20

TC19

TC18

TC17

TC16

00000000

RW

Byte 2

E6D0

1

GPIFTCB1[7]

GPIF Transaction Count

TC15

TC14

TC13

TC12

TC11

TC10

TC9

TC8

00000000

RW

Byte 1

E6D1

1

GPIFTCB0[7]

GPIF Transaction Count

TC7

TC6

TC5

TC4

TC3

TC2

TC1

TC0

00000001

RW

Byte 0

2

reserved

00000000

RW

reserved

reserved

1

E6D2

1

EP2GPIFFLGSEL[7]

Endpoint 2 GPIF Flag

0

0

0

0

0

0

FS1

FS0

00000000

RW

select

E6D3

1

EP2GPIFPFSTOP

Endpoint 2 GPIF stop

0

0

0

0

0

0

0

FIFO2FLAG

00000000

RW

transaction on prog. flag

E6D4

1

EP2GPIFTRIG[7]

Endpoint 2 GPIF Trigger

x

x

x

x

x

x

x

x

xxxxxxxx

W

3

reserved

reserved

reserved

E6DA

1

EP4GPIFFLGSEL[7]

Endpoint 4 GPIF Flag

0

0

0

0

0

0

FS1

FS0

00000000

RW

select

E6DB

1

EP4GPIFPFSTOP

Endpoint 4 GPIF stop

0

0

0

0

0

0

0

FIFO4FLAG

00000000

RW

transaction on GPIF Flag

E6DC

1

EP4GPIFTRIG[7]

Endpoint 4 GPIF Trigger

x

x

x

x

x

x

x

x

xxxxxxxx

W

3

reserved

reserved

reserved

E6E2

1

EP6GPIFFLGSEL[7]

Endpoint 6 GPIF Flag

0

0

0

0

0

0

FS1

FS0

00000000

RW

select

E6E3

1

EP6GPIFPFSTOP

Endpoint 6 GPIF stop

0

0

0

0

0

0

0

FIFO6FLAG

00000000

RW

transaction on prog. flag

E6E4

1

EP6GPIFTRIG[7]

Endpoint 6 GPIF Trigger

x

x

x

x

x

x

x

x

xxxxxxxx

W

3

reserved

reserved

reserved

E6EA

1

EP8GPIFFLGSEL[7]

Endpoint 8 GPIF Flag

0

0

0

0

0

0

FS1

FS0

00000000

RW

select

E6EB

1

EP8GPIFPFSTOP

Endpoint 8 GPIF stop

0

0

0

0

0

0

0

FIFO8FLAG

00000000

RW

transaction on prog. flag

E6EC

1

EP8GPIFTRIG[7]

Endpoint 8 GPIF Trigger

x

x

x

x

x

x

x

x

xxxxxxxx

W

3

reserved

E6F0

1

XGPIFSGLDATH

GPIF Data H

D15

D14

D13

D12

D11

D10

D9

D8

xxxxxxxx

RW

(16-bit mode only)

E6F1

1

XGPIFSGLDATLX

Read/Write GPIF Data L &

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

trigger transaction

E6F2

1

XGPIFSGLDATL-

Read GPIF Data L, no

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

R

NOX

transaction trigger

E6F3

1

GPIFREADYCFG

Internal RDY, Sync/Async,

INTRDY

SAS

TCXRDY5

0

0

0

0

0

00000000

bbbrrrrr

RDY pin states

E6F4

1

GPIFREADYSTAT

GPIF Ready Status

0

0

RDY5

RDY4

RDY3

RDY2

RDY1

RDY0

00xxxxxx

R

E6F5

1

GPIFABORT

Abort GPIF Waveforms

x

x

x

x

x

x

x

x

xxxxxxxx

W

E6F6

2

reserved

ENDPOINT BUFFERS

E740

64

EP0BUF

EP0-IN/-OUT buffer

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

E780

64

EP10UTBUF

EP1-OUT buffer

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

E7C0

64

EP1INBUF

EP1-IN buffer

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

2048

reserved

RW

F000

1024

EP2FIFOBUF

512/1024-byte EP 2/slave

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

FIFO buffer (IN or OUT)

F400

512

EP4FIFOBUF

512 byte EP 4/slave FIFO

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

buffer (IN or OUT)

F600

512

reserved

F800

1024

EP6FIFOBUF

512/1024-byte EP 6/slave

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

FIFO buffer (IN or OUT)

FC00

512

EP8FIFOBUF

512 byte EP 8/slave FIFO

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

buffer (IN or OUT)

FE00

512

reserved

xxxx

I²C Configuration Byte

0

DISCON

0

0

0

0

0

400KHZ

xxxxxxxx

n/a

[10]

Special Function Registers (SFRs)

80

1

IOA[9]

Port A (bit addressable)

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

81

1

SP

Stack Pointer

D7

D6

D5

D4

D3

D2

D1

D0

00000111

RW

82

1

DPL0

Data Pointer 0 L

A7

A6

A5

A4

A3

A2

A1

A0

00000000

RW

Document #: 001-04247 Rev. *D

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Contents CY7C68034 Only Silicon Features CY7C68033/CY7C68034 Silicon FeaturesBlock Diagram CY7C68033 Only Silicon FeaturesOverview Default Nand Firmware FeaturesApplications Clock Frequency USB Signaling SpeedFunctional Overview Special Function RegistersMpage INT4CLR OEA IOA IOB IOC IODPSW ACC Exif INT2CLR IOE SBUF1 OEB DPL1 OEC DPH1 OED DPS OEEDefault Silicon ID Values Default Silicon ID Values Default VID/PID/DIDBus-powered Applications ReNumerationPriority INT2VEC Value Source INT2 USB InterruptsUSB Interrupt Table for INT2 FIFO/GPIF Interrupt INT4Reset and Wakeup Reset PinProgram/Data RAM Reset Timing Values ConditionRegister Addresses Default Full-Speed Alternate Settings2 Endpoint RAMExternal Fifo Interface Default High-Speed Alternate Settings2Gpif ECC Generation5 Autopointer AccessI2C Controller Feature programmable polarity Pin AssignmentsCY7C68033/CY7C68034 Nand NX2LP-Flex Pin Descriptions 56 QFN Default PinPin Default Description Name TypePort a Port B Port DPower and Ground GroundRegister Summary NX2LP-Flex Register SummaryRegister can only be reset, it cannot be set Nakirq EP0CS E6CD Flowstbperiod SEL Absolute Maximum Ratings Operating ConditionsAC Electrical Characteristics DC CharacteristicsUSB Transceiver Slave Fifo Asynchronous Read Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Output EnableSlave Fifo Address to Flags/Data Sequence Diagram of a Single and Burst Asynchronous Read FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeRD/WR/PKTEND to FIFOADR10 Hold Time Sequence Diagram Slave Fifo Asynchronous AddressSequence Diagram of a Single and Burst Asynchronous Write Slave Fifo Asynchronous Write Sequence and Timing Diagram13Package Diagram Ordering InformationPCB Layout Recommendations16 Quad Flat Package No Leads QFN Package Design NotesPlot of the Solder Mask White Area Document History Issue Date Orig. Description of ChangeREV ECN no