Cypress manual CY7C68033/CY7C68034

Page 13

CY7C68033/CY7C68034

Figure 10. CY7C68033/CY7C68034 56-pin QFN Pin Assignment

VCC *WAKEUP PD0/FD8 PD1/FD9 PD2/FD10 PD3/FD11 PD4/FD12 PD5/FD13 PD6/FD14 PD7/FD15 GND GPIO9 VCC GND

RDY0/*SLRD

RDY1/*SLWR

AVCC XTALOUT XTALIN AGND AVCC

CY7C68033/CY7C68034

RESET# GND PA7/*FLAGD/SLCS# PA6/*PKTEND PA5/FIFOADR1 PA4/FIFOADR0 PA3/*WU2

DPLUS

DMINUS

AGND

VCC

GND

GPIO8

RESERVED#

56-pin QFN

PA2/*SLOE

PA1/INT1#

PA0/INT0#

VCC CTL2/*FLAGC CTL1/*FLAGB CTL0/*FLAGA

GND

VCC

GND

PB7/FD7

PB6/FD6

PB5/FD5

PB4/FD4

PB3/FD3

PB2/FD2

PB1/FD1

PB0/FD0

VCC

SDATA

SCL

Document #: 001-04247 Rev. *D

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Contents Block Diagram CY7C68033/CY7C68034 Silicon FeaturesCY7C68034 Only Silicon Features CY7C68033 Only Silicon FeaturesOverview Default Nand Firmware FeaturesApplications Functional Overview USB Signaling SpeedClock Frequency Special Function RegistersPSW ACC Exif INT2CLR IOE SBUF1 IOA IOB IOC IODMpage INT4CLR OEA OEB DPL1 OEC DPH1 OED DPS OEEBus-powered Applications Default Silicon ID Values Default VID/PID/DIDDefault Silicon ID Values ReNumerationUSB Interrupt Table for INT2 INT2 USB InterruptsPriority INT2VEC Value Source FIFO/GPIF Interrupt INT4Reset Pin Reset and WakeupProgram/Data RAM Reset Timing Values ConditionRegister Addresses Endpoint RAM Default Full-Speed Alternate Settings2External Fifo Interface Default High-Speed Alternate Settings2Gpif ECC Generation5 Autopointer AccessI2C Controller Pin Assignments Feature programmable polarityCY7C68033/CY7C68034 Pin Default Description Name NX2LP-Flex Pin Descriptions 56 QFN Default PinNand TypePort a Port D Port BGround Power and GroundNX2LP-Flex Register Summary Register SummaryRegister can only be reset, it cannot be set Nakirq EP0CS E6CD Flowstbperiod SEL Operating Conditions Absolute Maximum RatingsAC Electrical Characteristics DC CharacteristicsUSB Transceiver Slave Fifo Asynchronous Write Slave Fifo Asynchronous ReadSlave Fifo Asynchronous Packet End Strobe Slave Fifo Output EnableSlave Fifo Address to Flags/Data RD/WR/PKTEND to FIFOADR10 Hold Time Sequence Diagram FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous AddressSlave Fifo Asynchronous Write Sequence and Timing Diagram13 Sequence Diagram of a Single and Burst Asynchronous WriteOrdering Information Package DiagramQuad Flat Package No Leads QFN Package Design Notes PCB Layout Recommendations16Plot of the Solder Mask White Area Document History Issue Date Orig. Description of ChangeREV ECN no