Cypress CY7C68034, CY7C68033 DC Characteristics, AC Electrical Characteristics, USB Transceiver

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CY7C68033/CY7C68034

DC Characteristics

Table 10.DC Characteristics

Parameter	Description	Conditions	Min.	Typ.	Max.	Unit
VCC	Supply Voltage		3.00	3.3	3.60	V
VCC Ramp Up	0 to 3.3V		200			μs
VIH	Input HIGH Voltage		2		5.25	V
VIL	Input LOW Voltage		–0.5		0.8	V
VIH_X	Crystal Input HIGH Voltage		2		5.25	V
VIL_X	Crystal Input LOW Voltage		–0.5		0.8	V
II	Input Leakage Current	0< VIN < VCC			±10	μA
VOH	Output Voltage HIGH	IOUT = 4 mA	2.4			V
VOL	Output LOW Voltage	IOUT = –4 mA			0.4	V
IOH	Output Current HIGH				4	mA
IOL	Output Current LOW				4	mA
CIN	Input Pin Capacitance	Except D+/D–			10	pF
		D+/D–			15	pF

I	Suspend Current	Connected		300	380[12]	μA
SUSP
	CY7C68034	Disconnected		100	150[12]	μA
	Suspend Current	Connected		0.5	1.2[12]	mA
	CY7C68033	Disconnected		0.3	1.0[12]	mA
ICC	Supply Current	8051 running, connected to USB HS		43		mA
		8051 running, connected to USB FS		35		mA

IUNCONFIG	Unconfigured Current	Before bMaxPower granted by host		43		mA
TRESET	Reset Time After Valid Power	VCC min = 3.0V	5.0			ms
	Pin Reset After powered on		200			μs

USB Transceiver

USB 2.0-compliant in full- and high-speed modes.

AC Electrical Characteristics

USB Transceiver

USB 2.0-compliant in full- and high-speed modes.

Note

12. Measured at Max VCC, 25°C.

Document #: 001-04247 Rev. *D

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Contents Block Diagram CY7C68033/CY7C68034 Silicon FeaturesCY7C68034 Only Silicon Features CY7C68033 Only Silicon FeaturesOverview Default Nand Firmware FeaturesApplications Functional Overview USB Signaling SpeedClock Frequency Special Function RegistersPSW ACC Exif INT2CLR IOE SBUF1 IOA IOB IOC IODMpage INT4CLR OEA OEB DPL1 OEC DPH1 OED DPS OEEBus-powered Applications Default Silicon ID Values Default VID/PID/DIDDefault Silicon ID Values ReNumerationUSB Interrupt Table for INT2 INT2 USB InterruptsPriority INT2VEC Value Source FIFO/GPIF Interrupt INT4Reset Pin Reset and WakeupProgram/Data RAM Reset Timing Values ConditionRegister Addresses Endpoint RAM Default Full-Speed Alternate Settings2External Fifo Interface Default High-Speed Alternate Settings2Gpif ECC Generation5 Autopointer AccessI2C Controller Pin Assignments Feature programmable polarityCY7C68033/CY7C68034 Pin Default Description Name NX2LP-Flex Pin Descriptions 56 QFN Default PinNand TypePort a Port D Port BGround Power and GroundNX2LP-Flex Register Summary Register SummaryRegister can only be reset, it cannot be set Nakirq EP0CS E6CD Flowstbperiod SEL Operating Conditions Absolute Maximum RatingsAC Electrical Characteristics DC CharacteristicsUSB Transceiver Slave Fifo Asynchronous Write Slave Fifo Asynchronous ReadSlave Fifo Asynchronous Packet End Strobe Slave Fifo Output EnableSlave Fifo Address to Flags/Data RD/WR/PKTEND to FIFOADR10 Hold Time Sequence Diagram FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous AddressSlave Fifo Asynchronous Write Sequence and Timing Diagram13 Sequence Diagram of a Single and Burst Asynchronous WriteOrdering Information Package DiagramQuad Flat Package No Leads QFN Package Design Notes PCB Layout Recommendations16Plot of the Solder Mask White Area Document History Issue Date Orig. Description of ChangeREV ECN no