Cypress CY7C68033 manual Ioa Iob Ioc Iod, PSW ACC Exif INT2CLR IOE SBUF1, Mpage INT4CLR OEA, Tcon

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CY7C68033/CY7C68034

Table 1. Special Function Registers

x	8x	9x	Ax	Bx	Cx	Dx	Ex	Fx
0	IOA	IOB	IOC	IOD	SCON1	PSW	ACC	B
1	SP	EXIF	INT2CLR	IOE	SBUF1
2	DPL0	MPAGE	INT4CLR	OEA
3	DPH0			OEB
4	DPL1			OEC
5	DPH1			OED
6	DPS			OEE
7	PCON

8	TCON	SCON0	IE	IP	T2CON	EICON	EIE	EIP

9	TMOD	SBUF0
A	TL0	AUTOPTRH1	EP2468STAT	EP01STAT	RCAP2L
B	TL1	AUTOPTRL1	EP24FIFOFLGS	GPIFTRIG	RCAP2H

C	TH0	RESERVED	EP68FIFOFLGS		TL2
D	TH1	AUTOPTRH2		GPIFSGLDATH	TH2

E	CKCON	AUTOPTRL2		GPIFSGLDATLX

F		RESERVED	AUTOPTRSET-UP	GPIFSGLDATLNOX

Buses

The NX2LP-Flex features an 8- or 16-bit ‘FIFO’ bidirectional data bus, multiplexed on I/O ports B and D.

The default firmware image implements an 8-bit data bus in GPIF Master mode. It is recommended that additional inter- faces added to the default firmware image use this 8-bit data bus.

Enumeration

During the start-up sequence, internal logic checks for the presence of NAND Flash with valid firmware. If valid firmware is found, the NX2LP-Flex loads it and operates according to the firmware. If no NAND Flash is detected, or if no valid firmware is found, the NX2LP-Flex uses the default values from internal ROM space for manufacturing mode operation. The two modes of operation are described in the section ”Normal Operation Mode” on page 5 and ”Manufacturing Mode” on page 5.

Document #: 001-04247 Rev. *D

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Contents CY7C68033/CY7C68034 Silicon Features Block DiagramCY7C68034 Only Silicon Features CY7C68033 Only Silicon FeaturesOverview Default Nand Firmware FeaturesApplications USB Signaling Speed Functional OverviewClock Frequency Special Function RegistersIOA IOB IOC IOD PSW ACC Exif INT2CLR IOE SBUF1Mpage INT4CLR OEA OEB DPL1 OEC DPH1 OED DPS OEEDefault Silicon ID Values Default VID/PID/DID Bus-powered ApplicationsDefault Silicon ID Values ReNumerationINT2 USB Interrupts USB Interrupt Table for INT2Priority INT2VEC Value Source FIFO/GPIF Interrupt INT4Reset and Wakeup Reset PinProgram/Data RAM Reset Timing Values ConditionRegister Addresses Default Full-Speed Alternate Settings2 Endpoint RAMExternal Fifo Interface Default High-Speed Alternate Settings2Gpif ECC Generation5 Autopointer AccessI2C Controller Feature programmable polarity Pin AssignmentsCY7C68033/CY7C68034 NX2LP-Flex Pin Descriptions 56 QFN Default Pin Pin Default Description NameNand TypePort a Port B Port DPower and Ground GroundRegister Summary NX2LP-Flex Register SummaryRegister can only be reset, it cannot be set Nakirq EP0CS E6CD Flowstbperiod SEL Absolute Maximum Ratings Operating ConditionsAC Electrical Characteristics DC CharacteristicsUSB Transceiver Slave Fifo Asynchronous Read Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Output EnableSlave Fifo Address to Flags/Data FIFOADR10 to SLRD/SLWR/PKTEND Setup Time RD/WR/PKTEND to FIFOADR10 Hold Time Sequence DiagramSequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous AddressSequence Diagram of a Single and Burst Asynchronous Write Slave Fifo Asynchronous Write Sequence and Timing Diagram13Package Diagram Ordering InformationPCB Layout Recommendations16 Quad Flat Package No Leads QFN Package Design NotesPlot of the Solder Mask White Area Document History Issue Date Orig. Description of ChangeREV ECN no