Cypress CY7C68033, CY7C68034 manual NX2LP-Flex Register Summary

CY7C68033/CY7C68034

Register Summary

NX2LP-Flex register bit definitions are described in the EZ-USB TRM in greater detail. Some registers that are listed here and in the TRM do not apply to the NX2LP-Flex. They are kept here for consistency reasons only. Registers that do not apply to the NX2LP-Flex should be left at their default power-up values.

Table 9. NX2LP-Flex Register Summary

Hex

Size

Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

GPIF Waveform Memories

E400

128

WAVEDATA

GPIF Waveform

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

Descriptor 0, 1, 2, 3 data

E480

128

reserved

GENERAL CONFIGURATION

E50D

GPCR2

General Purpose Configu-

reserved

reserved

reserved

FULL_SPEE

reserved

reserved

reserved

reserved

00000000

R

ration Register 2

D_ONLY

E600

1

CPUCS

CPU Control & Status

0

0

PORTCSTB

CLKSPD1

CLKSPD0

CLKINV

CLKOE

8051RES

00000010

rrbbbbbr

E601

1

IFCONFIG

Interface Configuration

1

3048MHZ

0

IFCLKPOL

ASYNC

GSTATE

IFCFG1

IFCFG0

10000000

RW

(Ports, GPIF, slave FIFOs)

E602

1

PINFLAGSAB[7]

Slave FIFO FLAGA and

FLAGB3

FLAGB2

FLAGB1

FLAGB0

FLAGA3

FLAGA2

FLAGA1

FLAGA0

00000000

RW

FLAGB Pin Configuration

E603

1

PINFLAGSCD[7]

Slave FIFO FLAGC and

FLAGD3

FLAGD2

FLAGD1

FLAGD0

FLAGC3

FLAGC2

FLAGC1

FLAGC0

00000000

RW

FLAGD Pin Configuration

E604

1

FIFORESET[7]

Restore FIFOS to default

NAKALL

0

0

0

EP3

EP2

EP1

EP0

xxxxxxxx

W

state

E605

1

BREAKPT

Breakpoint Control

0

0

0

0

BREAK

BPPULSE

BPEN

0

00000000

rrrrbbbr

E606

1

BPADDRH

Breakpoint Address H

A15

A14

A13

A12

A11

A10

A9

A8

xxxxxxxx

RW

E607

1

BPADDRL

Breakpoint Address L

A7

A6

A5

A4

A3

A2

A1

A0

xxxxxxxx

RW

E608

1

UART230

230 Kbaud internally

0

0

0

0

0

0

230UART1

230UART0

00000000

rrrrrrbb

generated ref. clock

E609

1

FIFOPINPOLAR[7]

Slave FIFO Interface pins

0

0

PKTEND

SLOE

SLRD

SLWR

EF

FF

00000000

rrbbbbbb

polarity

E60A

1

REVID

Chip Revision

rv7

rv6

rv5

rv4

rv3

rv2

rv1

rv0

RevA

R

00000001

E60B

1

REVCTL[7]

Chip Revision Control

0

0

0

0

0

0

dyn_out

enh_pkt

00000000

rrrrrrbb

UDMA

E60C

1

GPIFHOLDAMOUNT

MSTB Hold Time

0

0

0

0

0

0

HOLDTIME1

HOLDTIME0

00000000

rrrrrrbb

(for UDMA)

3

reserved

ENDPOINT CONFIGURATION

E610

1

EP1OUTCFG

Endpoint 1-OUT

VALID

0

TYPE1

TYPE0

0

0

0

0

10100000

brbbrrrr

Configuration

E611

1

EP1INCFG

Endpoint 1-IN

VALID

0

TYPE1

TYPE0

0

0

0

0

10100000

brbbrrrr

Configuration

E612

1

EP2CFG

Endpoint 2 Configuration

VALID

DIR

TYPE1

TYPE0

SIZE

0

BUF1

BUF0

10100010

bbbbbrbb

E613

1

EP4CFG

Endpoint 4 Configuration

VALID

DIR

TYPE1

TYPE0

0

0

0

0

10100000

bbbbrrrr

E614

1

EP6CFG

Endpoint 6 Configuration

VALID

DIR

TYPE1

TYPE0

SIZE

0

BUF1

BUF0

11100010

bbbbbrbb

E615

1

EP8CFG

Endpoint 8 Configuration

VALID

DIR

TYPE1

TYPE0

0

0

0

0

11100000

bbbbrrrr

2

reserved

E618

1

EP2FIFOCFG[7]

Endpoint 2/slave FIFO

0

INFM1

OEP1

AUTOOUT

AUTOIN

ZEROLENIN

0

WORDWIDE

00000101

rbbbbbrb

configuration

E619

1

EP4FIFOCFG[7]

Endpoint 4/slave FIFO

0

INFM1

OEP1

AUTOOUT

AUTOIN

ZEROLENIN

0

WORDWIDE

00000101

rbbbbbrb

configuration

E61A

1

EP6FIFOCFG[7]

Endpoint 6/slave FIFO

0

INFM1

OEP1

AUTOOUT

AUTOIN

ZEROLENIN

0

WORDWIDE

00000101

rbbbbbrb

configuration

E61B

1

EP8FIFOCFG[7]

Endpoint 8/slave FIFO

0

INFM1

OEP1

AUTOOUT

AUTOIN

ZEROLENIN

0

WORDWIDE

00000101

rbbbbbrb

configuration

E61C

4

reserved

E620

1

EP2AUTOINLENH[7

Endpoint 2 AUTOIN

0

0

0

0

0

PL10

PL9

PL8

00000010

rrrrrbbb

Packet Length H

E621

1

EP2AUTOINLENL[7]

Endpoint 2 AUTOIN

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

00000000

RW

Packet Length L

E622

1

EP4AUTOINLENH[7]

Endpoint 4 AUTOIN

0

0

0

0

0

0

PL9

PL8

00000010

rrrrrrbb

Packet Length H

E623

1

EP4AUTOINLENL[7]

Endpoint 4 AUTOIN

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

00000000

RW

Packet Length L

E624

1

EP6AUTOINLENH[7]

Endpoint 6 AUTOIN

0

0

0

0

0

PL10

PL9

PL8

00000010

rrrrrbbb

Packet Length H

E625

1

EP6AUTOINLENL[7]

Endpoint 6 AUTOIN

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

00000000

RW

Packet Length L

E626

1

EP8AUTOINLENH[7]

Endpoint 8 AUTOIN

0

0

0

0

0

0

PL9

PL8

00000010

rrrrrrbb

Packet Length H

E627

1

EP8AUTOINLENL[7]

Endpoint 8 AUTOIN

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

00000000

RW

Packet Length L

E628

1

ECCCFG

ECC Configuration

0

0

0

0

0

0

0

ECCM

00000000

rrrrrrrb

Note

7. Read and writes to these registers may require synchronization delay, see the Technical Reference Manual for “Synchronization Delay.”
Document #: 001-04247 Rev. *D	Page 18 of 33
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