Cypress CY7C68034, CY7C68033 Slave Fifo Asynchronous Packet End Strobe, Slave Fifo Output Enable

Page 27

CY7C68033/CY7C68034

Slave FIFO Asynchronous Packet End Strobe

Figure 13. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[9]

PKTEND

tPEpwl

tPEpwh

FLAGS

tXFLG

Table 13.Slave FIFO Asynchronous Packet End Strobe Parameters[15]

Parameter

Description

Min.

Max.

Unit

tPEpwl

PKTEND Pulse Width LOW

50

 

ns

tPWpwh

PKTEND Pulse Width HIGH

50

 

ns

tXFLG

PKTEND to FLAGS Output Propagation Delay

 

115

ns

Slave FIFO Output Enable

Figure 14. Slave FIFO Output Enable Timing Diagram[13]

SLOE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tOEon

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tOEoff

Table 14.Slave FIFO Output Enable Parameters

Parameter

Description

Min.

Max.

Unit

tOEon

SLOE Assert to FIFO DATA Output

 

10.5

ns

tOEoff

SLOE Deassert to FIFO DATA Hold

 

10.5

ns

Slave FIFO Address to Flags/Data

Figure 15. Slave FIFO Address to Flags/Data Timing Diagram[13]

FIFOADR [1.0]

tXFLG

FLAGS

tXFD

DATA

N

 

 

N+1

Table 15.Slave FIFO Address to Flags/Data Parameters

 

Parameter

Description

Min.

Max.

Unit

 

tXFLG

FIFOADR[1:0] to FLAGS Output Propagation Delay

 

10.7

ns

 

tXFD

FIFOADR[1:0] to FIFODATA Output Propagation Delay

 

14.3

ns

Document #: 001-04247 Rev. *D

 

 

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Contents CY7C68033 Only Silicon Features CY7C68033/CY7C68034 Silicon FeaturesBlock Diagram CY7C68034 Only Silicon FeaturesDefault Nand Firmware Features OverviewApplications Special Function Registers USB Signaling SpeedFunctional Overview Clock FrequencyOEB DPL1 OEC DPH1 OED DPS OEE IOA IOB IOC IODPSW ACC Exif INT2CLR IOE SBUF1 Mpage INT4CLR OEAReNumeration Default Silicon ID Values Default VID/PID/DIDBus-powered Applications Default Silicon ID ValuesFIFO/GPIF Interrupt INT4 INT2 USB InterruptsUSB Interrupt Table for INT2 Priority INT2VEC Value SourceReset Pin Reset and WakeupReset Timing Values Condition Program/Data RAMRegister Addresses Endpoint RAM Default Full-Speed Alternate Settings2Default High-Speed Alternate Settings2 External Fifo InterfaceGpif Autopointer Access ECC Generation5I2C Controller Pin Assignments Feature programmable polarityCY7C68033/CY7C68034 Type NX2LP-Flex Pin Descriptions 56 QFN Default PinPin Default Description Name NandPort a Port D Port BGround Power and GroundNX2LP-Flex Register Summary Register SummaryRegister can only be reset, it cannot be set Nakirq EP0CS E6CD Flowstbperiod SEL Operating Conditions Absolute Maximum RatingsDC Characteristics AC Electrical CharacteristicsUSB Transceiver Slave Fifo Asynchronous Write Slave Fifo Asynchronous ReadSlave Fifo Output Enable Slave Fifo Asynchronous Packet End StrobeSlave Fifo Address to Flags/Data Slave Fifo Asynchronous Address FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeRD/WR/PKTEND to FIFOADR10 Hold Time Sequence Diagram Sequence Diagram of a Single and Burst Asynchronous ReadSlave Fifo Asynchronous Write Sequence and Timing Diagram13 Sequence Diagram of a Single and Burst Asynchronous WriteOrdering Information Package DiagramQuad Flat Package No Leads QFN Package Design Notes PCB Layout Recommendations16Plot of the Solder Mask White Area Issue Date Orig. Description of Change Document HistoryREV ECN no