Cypress CY7C68034, CY7C68033 Document History, REV ECN no, Issue Date Orig. Description of Change

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CY7C68033/CY7C68034

Document History Page

Document Title: CY7C68033/CY7C68034 EZ-USB NX2LP-Flex™ Flexible USB NAND Flash Controller

Document #: 001-04247 Rev. *D

	REV.	ECN NO.	Issue Date	Orig. of	Description of Change
	REV.	ECN NO.	Issue Date	Change	Description of Change
				Change

	**	388499	See ECN	GIR	Preliminary draft

	*A	394699	See ECN	XUT	Minor Change: Upload data sheet to external website. Publicly announcing the
					parts. No physical changes to document were made
	*B	400518	See ECN	GIR	Took ‘Preliminary’ off the top of all pages. Corrected the first bulleted item.
					Corrected Figure 3-2 caption. Added new logo
	*C	433952	See ECN	RGL	Added I2C functionality
	*D	498295	See ECN	KKU	Updated Data sheet format
					Changed In/Output reference from I/O to IO
					Changed set-up to setup
					Changed IFCLK and CLKOUT pins to GPIO8 and GPIO9. Removed external
					IFCLK

Document #: 001-04247 Rev. *D

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Contents Block Diagram CY7C68033/CY7C68034 Silicon FeaturesCY7C68034 Only Silicon Features CY7C68033 Only Silicon FeaturesDefault Nand Firmware Features OverviewApplications Functional Overview USB Signaling SpeedClock Frequency Special Function RegistersPSW ACC Exif INT2CLR IOE SBUF1 IOA IOB IOC IODMpage INT4CLR OEA OEB DPL1 OEC DPH1 OED DPS OEEBus-powered Applications Default Silicon ID Values Default VID/PID/DIDDefault Silicon ID Values ReNumerationUSB Interrupt Table for INT2 INT2 USB InterruptsPriority INT2VEC Value Source FIFO/GPIF Interrupt INT4Reset Pin Reset and WakeupReset Timing Values Condition Program/Data RAMRegister Addresses Endpoint RAM Default Full-Speed Alternate Settings2Default High-Speed Alternate Settings2 External Fifo InterfaceGpif Autopointer Access ECC Generation5I2C Controller Pin Assignments Feature programmable polarityCY7C68033/CY7C68034 Pin Default Description Name NX2LP-Flex Pin Descriptions 56 QFN Default PinNand TypePort a Port D Port BGround Power and GroundNX2LP-Flex Register Summary Register SummaryRegister can only be reset, it cannot be set Nakirq EP0CS E6CD Flowstbperiod SEL Operating Conditions Absolute Maximum RatingsDC Characteristics AC Electrical CharacteristicsUSB Transceiver Slave Fifo Asynchronous Write Slave Fifo Asynchronous ReadSlave Fifo Output Enable Slave Fifo Asynchronous Packet End StrobeSlave Fifo Address to Flags/Data RD/WR/PKTEND to FIFOADR10 Hold Time Sequence Diagram FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous AddressSlave Fifo Asynchronous Write Sequence and Timing Diagram13 Sequence Diagram of a Single and Burst Asynchronous WriteOrdering Information Package DiagramQuad Flat Package No Leads QFN Package Design Notes PCB Layout Recommendations16Plot of the Solder Mask White Area Issue Date Orig. Description of Change Document HistoryREV ECN no