Cypress CY7C68033, CY7C68034 manual Overview, Applications, Default Nand Firmware Features

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CY7C68033/CY7C68034

Default NAND Firmware Features

Because the NX2LP-Flex™ is intended for NAND Flash-based USB mass storage applications, a default firmware image is included in the development kit with the following features:

High (480-Mbps) or full (12-Mbps) speed USB support

Both common NAND page sizes supported

512 bytes for up to 1 Gb capacity

2K bytes for up to 8 Gb capacity

12 configurable general-purpose I/O (GPIO) pins

2 dedicated chip enable (CE#) pins

6 configurable CE#/GPIO pins

Up to 8 NAND Flash single-device (single-die) chips are supported

Up to 4 NAND Flash dual-device (dual-die) chips are supported

Compile option allows unused CE# pins to be config- ured as GPIOs

4 dedicated GPIO pins

Industry standard ECC NAND Flash correction

1-bit per 256-bit correction

2-bit error detection

Industry standard (SmartMedia) page management for wear leveling algorithm, bad block handling, and Physical to Logical management.

8-bit NAND Flash interface support

Support for 30-ns, 50-ns, and 100-ns NAND Flash timing

Complies with the USB Mass Storage Class Specification revision 1.0

The default firmware image implements a USB 2.0 NAND Flash controller. This controller adheres to the Mass Storage Class Bulk-Only Transport Specification. The USB port of the NX2LP-Flex is connected to a host computer directly or via the downstream port of a USB hub. Host software issues commands and data to the NX2LP-Flex and receives status and data from the NX2LP-Flex using standard USB protocol.

The default firmware image supports industry leading 8-bit NAND Flash interfaces and both common NAND page sizes of 512 and 2k bytes. Up to eight chip enable pins allow the NX2LP-Flex to be connected to up to eight single- or four dual-die NAND Flash chips.

Complete source code and documentation for the default firmware image are included in the NX2LP-Flex development kit to enable customization for meeting design requirements. Additionally, compile options for the default firmware allow for

quick configuration of some features to decrease design effort and increase time-to-market advantages.

Overview

Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB NX2LP-Flex (CY7C68033/CY7C68034) is a firmware-based, programmable version of the EZ-USB NX2LP(CY7C68023/CY7C68024), which is a fixed-function, low-power USB 2.0 NAND Flash controller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost-effective solution that enables feature-rich NAND Flash-based applications.

The ingenious architecture of NX2LP-Flex results in USB data transfer rates of over 53 Mbytes per second, the maximum-allowable USB 2.0 bandwidth, while still using a low-cost 8051 microcontroller in a small 56-pin QFN package. Because it incorporates the USB 2.0 transceiver, the NX2LP-Flex is more economical, providing a smaller footprint solution than external USB 2.0 SIE or transceiver implemen- tations. With EZ-USB NX2LP-Flex, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol, freeing the embedded microcontroller for application-specific functions and decreasing development time while ensuring USB compatibility.

The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8- or 16-bit data bus) provide an easy and glueless interface to popular interfaces such as UTOPIA, EPP, I2C, PCMCIA, and most DSP processors.

Applications

The NX2LP-Flex allows designers to add extra functionality to basic NAND Flash mass storage designs, or to interface them with other peripheral devices. Applications may include:

NAND Flash-based GPS devices

NAND Flash-based DVB video capture devices

Wireless pointer/presenter tools with NAND Flash storage

NAND Flash-based MPEG/TV conversion devices

Legacy conversion devices with NAND Flash storage

NAND Flash-based cameras

NAND Flash mass storage device with biometric (e.g., fingerprint) security

Home PNA devices with NAND Flash storage

Wireless LAN with NAND Flash storage

NAND Flash-based MP3 players

LAN networking with NAND Flash storage

Document #: 001-04247 Rev. *D

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Contents CY7C68034 Only Silicon Features CY7C68033/CY7C68034 Silicon FeaturesBlock Diagram CY7C68033 Only Silicon FeaturesApplications Default Nand Firmware FeaturesOverview Clock Frequency USB Signaling SpeedFunctional Overview Special Function RegistersMpage INT4CLR OEA IOA IOB IOC IODPSW ACC Exif INT2CLR IOE SBUF1 OEB DPL1 OEC DPH1 OED DPS OEEDefault Silicon ID Values Default Silicon ID Values Default VID/PID/DIDBus-powered Applications ReNumerationPriority INT2VEC Value Source INT2 USB InterruptsUSB Interrupt Table for INT2 FIFO/GPIF Interrupt INT4Reset and Wakeup Reset PinRegister Addresses Reset Timing Values ConditionProgram/Data RAM Default Full-Speed Alternate Settings2 Endpoint RAMGpif Default High-Speed Alternate Settings2External Fifo Interface I2C Controller Autopointer AccessECC Generation5 Feature programmable polarity Pin AssignmentsCY7C68033/CY7C68034 Nand NX2LP-Flex Pin Descriptions 56 QFN Default PinPin Default Description Name TypePort a Port B Port DPower and Ground GroundRegister Summary NX2LP-Flex Register SummaryRegister can only be reset, it cannot be set Nakirq EP0CS E6CD Flowstbperiod SEL Absolute Maximum Ratings Operating ConditionsUSB Transceiver DC CharacteristicsAC Electrical Characteristics Slave Fifo Asynchronous Read Slave Fifo Asynchronous WriteSlave Fifo Address to Flags/Data Slave Fifo Output EnableSlave Fifo Asynchronous Packet End Strobe Sequence Diagram of a Single and Burst Asynchronous Read FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeRD/WR/PKTEND to FIFOADR10 Hold Time Sequence Diagram Slave Fifo Asynchronous AddressSequence Diagram of a Single and Burst Asynchronous Write Slave Fifo Asynchronous Write Sequence and Timing Diagram13Package Diagram Ordering InformationPCB Layout Recommendations16 Quad Flat Package No Leads QFN Package Design NotesPlot of the Solder Mask White Area REV ECN no Issue Date Orig. Description of ChangeDocument History