Cypress CY7C68034, CY7C68033 manual Register can only be reset, it cannot be set

Page 19

CY7C68033/CY7C68034

Table 9. NX2LP-Flex Register Summary (continued)

Hex

Size

Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

E629

1

ECCRESET

ECC Reset

x

x

x

x

x

x

x

x

00000000

W

E62A

1

ECC1B0

ECC1 Byte 0 Address

LINE15

LINE14

LINE13

LINE12

LINE11

LINE10

LINE9

LINE8

00000000

R

E62B

1

ECC1B1

ECC1 Byte 1 Address

LINE7

LINE6

LINE5

LINE4

LINE3

LINE2

LINE1

LINE0

00000000

R

E62C

1

ECC1B2

ECC1 Byte 2 Address

COL5

COL4

COL3

COL2

COL1

COL0

LINE17

LINE16

00000000

R

E62D

1

ECC2B0

ECC2 Byte 0 Address

LINE15

LINE14

LINE13

LINE12

LINE11

LINE10

LINE9

LINE8

00000000

R

E62E

1

ECC2B1

ECC2 Byte 1 Address

LINE7

LINE6

LINE5

LINE4

LINE3

LINE2

LINE1

LINE0

00000000

R

E62F

1

ECC2B2

ECC2 Byte 2 Address

COL5

COL4

COL3

COL2

COL1

COL0

0

0

00000000

R

E630

1

EP2FIFOPFH[7]

Endpoint 2/slave FIFO

DECIS

PKTSTAT

IN:PKTS[2]

IN:PKTS[1]

IN:PKTS[0]

0

PFC9

PFC8

10001000

bbbbbrbb

H.S.

 

 

Programmable Flag H

 

 

OUT:PFC12

OUT:PFC11

OUT:PFC10

 

 

 

 

 

E630

1

EP2FIFOPFH[7]

Endpoint 2/slave FIFO

DECIS

PKTSTAT

OUT:PFC12

OUT:PFC11

OUT:PFC10

0

PFC9

IN:PKTS[2]

10001000

bbbbbrbb

F.S.

 

 

Programmable Flag H

 

 

 

 

 

 

 

OUT:PFC8

 

 

E631

1

EP2FIFOPFL[7]

Endpoint 2/slave FIFO

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

H.S.

 

 

Programmable Flag L

 

 

 

 

 

 

 

 

 

 

E631

1

EP2FIFOPFL[7]

Endpoint 2/slave FIFO

IN:PKTS[1]

IN:PKTS[0]

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

F.S

 

 

Programmable Flag L

OUT:PFC7

OUT:PFC6

 

 

 

 

 

 

 

 

E632

1

EP4FIFOPFH[7]

Endpoint 4/slave FIFO

DECIS

PKTSTAT

0

IN: PKTS[1]

IN: PKTS[0]

0

0

PFC8

10001000

bbrbbrrb

H.S.

 

 

Programmable Flag H

 

 

 

OUT:PFC10

OUT:PFC9

 

 

 

 

 

E632

1

EP4FIFOPFH[7]

Endpoint 4/slave FIFO

DECIS

PKTSTAT

0

OUT:PFC10

OUT:PFC9

0

0

PFC8

10001000

bbrbbrrb

F.S

 

 

Programmable Flag H

 

 

 

 

 

 

 

 

 

 

E633

1

EP4FIFOPFL[7]

Endpoint 4/slave FIFO

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

H.S.

 

 

Programmable Flag L

 

 

 

 

 

 

 

 

 

 

E633

1

EP4FIFOPFL[7]

Endpoint 4/slave FIFO

IN: PKTS[1]

IN: PKTS[0]

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

F.S

 

 

Programmable Flag L

OUT:PFC7

OUT:PFC6

 

 

 

 

 

 

 

 

E634

1

EP6FIFOPFH[7]

Endpoint 6/slave FIFO

DECIS

PKTSTAT

IN:PKTS[2]

IN:PKTS[1]

IN:PKTS[0]

0

PFC9

PFC8

00001000

bbbbbrbb

H.S.

 

 

Programmable Flag H

 

 

OUT:PFC12

OUT:PFC11

OUT:PFC10

 

 

 

 

 

E634

1

EP6FIFOPFH[7]

Endpoint 6/slave FIFO

DECIS

PKTSTAT

OUT:PFC12

OUT:PFC11

OUT:PFC10

0

PFC9

IN:PKTS[2]

00001000

bbbbbrbb

F.S

 

 

Programmable Flag H

 

 

 

 

 

 

 

OUT:PFC8

 

 

E635

1

EP6FIFOPFL[7]

Endpoint 6/slave FIFO

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

H.S.

 

 

Programmable Flag L

 

 

 

 

 

 

 

 

 

 

E635

1

EP6FIFOPFL[7]

Endpoint 6/slave FIFO

IN:PKTS[1]

IN:PKTS[0]

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

F.S

 

 

Programmable Flag L

OUT:PFC7

OUT:PFC6

 

 

 

 

 

 

 

 

E636

1

EP8FIFOPFH[7]

Endpoint 8/slave FIFO

DECIS

PKTSTAT

0

IN: PKTS[1]

IN: PKTS[0]

0

0

PFC8

00001000

bbrbbrrb

H.S.

 

 

Programmable Flag H

 

 

 

OUT:PFC10

OUT:PFC9

 

 

 

 

 

E636

1

EP8FIFOPFH[7]

Endpoint 8/slave FIFO

DECIS

PKTSTAT

0

OUT:PFC10

OUT:PFC9

0

0

PFC8

00001000

bbrbbrrb

F.S

 

 

Programmable Flag H

 

 

 

 

 

 

 

 

 

 

E637

1

EP8FIFOPFL[7]

Endpoint 8/slave FIFO

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

H.S.

 

 

Programmable Flag L

 

 

 

 

 

 

 

 

 

 

E637

1

EP8FIFOPFL[7]

Endpoint 8/slave FIFO

IN: PKTS[1]

IN: PKTS[0]

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

F.S

 

 

Programmable Flag L

OUT:PFC7

OUT:PFC6

 

 

 

 

 

 

 

 

 

8

reserved

 

 

 

 

 

 

 

 

 

 

 

E640

1

EP2ISOINPKTS

EP2 (if ISO) IN Packets

AADJ

0

0

0

0

0

INPPF1

INPPF0

00000001

brrrrrbb

 

 

 

per frame (1-3)

 

 

 

 

 

 

 

 

 

 

E641

1

EP4ISOINPKTS

EP4 (if ISO) IN Packets

AADJ

0

0

0

0

0

INPPF1

INPPF0

00000001

brrrrrrr

 

 

 

per frame (1-3)

 

 

 

 

 

 

 

 

 

 

E642

1

EP6ISOINPKTS

EP6 (if ISO) IN Packets

AADJ

0

0

0

0

0

INPPF1

INPPF0

00000001

brrrrrbb

 

 

 

per frame (1-3)

 

 

 

 

 

 

 

 

 

 

E643

1

EP8ISOINPKTS

EP8 (if ISO) IN Packets

AADJ

0

0

0

0

0

INPPF1

INPPF0

00000001

brrrrrrr

 

 

 

per frame (1-3)

 

 

 

 

 

 

 

 

 

 

E644

4

reserved

 

 

 

 

 

 

 

 

 

 

 

E648

1

INPKTEND[7]

Force IN Packet End

Skip

0

0

0

EP3

EP2

EP1

EP0

xxxxxxxx

W

E649

7

OUTPKTEND[7]

Force OUT Packet End

Skip

0

0

0

EP3

EP2

EP1

EP0

xxxxxxxx

W

 

 

INTERRUPTS

 

 

 

 

 

 

 

 

 

 

 

E650

1

EP2FIFOIE[7]

Endpoint 2 slave FIFO

0

0

0

0

EDGEPF

PF

EF

FF

00000000

RW

 

 

 

Flag Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E651

1

EP2FIFOIRQ[7,8]

Endpoint 2 slave FIFO

0

0

0

0

0

PF

EF

FF

00000000

rrrrrbbb

 

 

 

Flag Interrupt Request

 

 

 

 

 

 

 

 

 

 

E652

1

EP4FIFOIE[7]

Endpoint 4 slave FIFO

0

0

0

0

EDGEPF

PF

EF

FF

00000000

RW

 

 

 

Flag Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E653

1

EP4FIFOIRQ[7,8]

Endpoint 4 slave FIFO

0

0

0

0

0

PF

EF

FF

00000000

rrrrrbbb

 

 

 

Flag Interrupt Request

 

 

 

 

 

 

 

 

 

 

E654

1

EP6FIFOIE[7]

Endpoint 6 slave FIFO

0

0

0

0

EDGEPF

PF

EF

FF

00000000

RW

 

 

 

Flag Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E655

1

EP6FIFOIRQ[7,8]

Endpoint 6 slave FIFO

0

0

0

0

0

PF

EF

FF

00000000

rrrrrbbb

 

 

 

Flag Interrupt Request

 

 

 

 

 

 

 

 

 

 

E656

1

EP8FIFOIE[7]

Endpoint 8 slave FIFO

0

0

0

0

EDGEPF

PF

EF

FF

00000000

RW

 

 

 

Flag Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E657

1

EP8FIFOIRQ[7,8]

Endpoint 8 slave FIFO

0

0

0

0

0

PF

EF

FF

00000000

rrrrrbbb

 

 

 

Flag Interrupt Request

 

 

 

 

 

 

 

 

 

 

E658

1

IBNIE

IN-BULK-NAK Interrupt

0

0

EP8

EP6

EP4

EP2

EP1

EP0

00000000

RW

 

 

 

Enable

 

 

 

 

 

 

 

 

 

 

E659

1

IBNIRQ[8]

IN-BULK-NAK interrupt

0

0

EP8

EP6

EP4

EP2

EP1

EP0

00xxxxxx

rrbbbbbb

 

 

 

Request

 

 

 

 

 

 

 

 

 

 

E65A

1

NAKIE

Endpoint Ping-NAK/IBN

EP8

EP6

EP4

EP2

EP1

EP0

0

IBN

00000000

RW

 

 

 

Interrupt Enable

 

 

 

 

 

 

 

 

 

 

Note

8. The register can only be reset, it cannot be set.

Document #: 001-04247 Rev. *D

Page 19 of 33

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Image 19
Contents CY7C68033 Only Silicon Features CY7C68033/CY7C68034 Silicon FeaturesBlock Diagram CY7C68034 Only Silicon FeaturesOverview Default Nand Firmware FeaturesApplications Special Function Registers USB Signaling SpeedFunctional Overview Clock FrequencyOEB DPL1 OEC DPH1 OED DPS OEE IOA IOB IOC IODPSW ACC Exif INT2CLR IOE SBUF1 Mpage INT4CLR OEAReNumeration Default Silicon ID Values Default VID/PID/DIDBus-powered Applications Default Silicon ID ValuesFIFO/GPIF Interrupt INT4 INT2 USB InterruptsUSB Interrupt Table for INT2 Priority INT2VEC Value SourceReset Pin Reset and WakeupProgram/Data RAM Reset Timing Values ConditionRegister Addresses Endpoint RAM Default Full-Speed Alternate Settings2External Fifo Interface Default High-Speed Alternate Settings2Gpif ECC Generation5 Autopointer AccessI2C Controller Pin Assignments Feature programmable polarityCY7C68033/CY7C68034 Type NX2LP-Flex Pin Descriptions 56 QFN Default PinPin Default Description Name NandPort a Port D Port BGround Power and GroundNX2LP-Flex Register Summary Register SummaryRegister can only be reset, it cannot be set Nakirq EP0CS E6CD Flowstbperiod SEL Operating Conditions Absolute Maximum RatingsAC Electrical Characteristics DC CharacteristicsUSB Transceiver Slave Fifo Asynchronous Write Slave Fifo Asynchronous ReadSlave Fifo Asynchronous Packet End Strobe Slave Fifo Output EnableSlave Fifo Address to Flags/Data Slave Fifo Asynchronous Address FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeRD/WR/PKTEND to FIFOADR10 Hold Time Sequence Diagram Sequence Diagram of a Single and Burst Asynchronous ReadSlave Fifo Asynchronous Write Sequence and Timing Diagram13 Sequence Diagram of a Single and Burst Asynchronous WriteOrdering Information Package DiagramQuad Flat Package No Leads QFN Package Design Notes PCB Layout Recommendations16Plot of the Solder Mask White Area Document History Issue Date Orig. Description of ChangeREV ECN no