Cypress CY7C68034, CY7C68033 manual EP0CS

Page 21

CY7C68033/CY7C68034

Table 9. NX2LP-Flex Register Summary (continued)

 

Hex

Size

Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

 

Default

Access

 

E69E

2

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

E6A0

1

EP0CS

Endpoint 0 Control and

HSNAK

0

0

0

0

0

BUSY

STALL

 

10000000

bbbbbbrb

 

 

 

 

Status

 

 

 

 

 

 

 

 

 

 

 

 

E6A1

1

EP1OUTCS

Endpoint 1 OUT Control

0

0

0

0

0

0

BUSY

STALL

 

00000000

bbbbbbrb

 

 

 

 

and Status

 

 

 

 

 

 

 

 

 

 

 

 

E6A2

1

EP1INCS

Endpoint 1 IN Control and

0

0

0

0

0

0

BUSY

STALL

 

00000000

bbbbbbrb

 

 

 

 

Status

 

 

 

 

 

 

 

 

 

 

 

 

E6A3

1

EP2CS

Endpoint 2 Control and

0

NPAK2

NPAK1

NPAK0

FULL

EMPTY

0

STALL

 

00101000

rrrrrrrb

 

 

 

 

Status

 

 

 

 

 

 

 

 

 

 

 

 

E6A4

1

EP4CS

Endpoint 4 Control and

0

0

NPAK1

NPAK0

FULL

EMPTY

0

STALL

 

00101000

rrrrrrrb

 

 

 

 

Status

 

 

 

 

 

 

 

 

 

 

 

 

E6A5

1

EP6CS

Endpoint 6 Control and

0

NPAK2

NPAK1

NPAK0

FULL

EMPTY

0

STALL

 

00000100

rrrrrrrb

 

 

 

 

Status

 

 

 

 

 

 

 

 

 

 

 

 

E6A6

1

EP8CS

Endpoint 8 Control and

0

0

NPAK1

NPAK0

FULL

EMPTY

0

STALL

 

00000100

rrrrrrrb

 

 

 

 

Status

 

 

 

 

 

 

 

 

 

 

 

 

E6A7

1

EP2FIFOFLGS

Endpoint 2 slave FIFO

0

0

0

0

0

PF

EF

FF

 

00000010

R

 

 

 

 

Flags

 

 

 

 

 

 

 

 

 

 

 

 

E6A8

1

EP4FIFOFLGS

Endpoint 4 slave FIFO

0

0

0

0

0

PF

EF

FF

 

00000010

R

 

 

 

 

Flags

 

 

 

 

 

 

 

 

 

 

 

 

E6A9

1

EP6FIFOFLGS

Endpoint 6 slave FIFO

0

0

0

0

0

PF

EF

FF

 

00000110

R

 

 

 

 

Flags

 

 

 

 

 

 

 

 

 

 

 

 

E6AA

1

EP8FIFOFLGS

Endpoint 8 slave FIFO

0

0

0

0

0

PF

EF

FF

 

00000110

R

 

 

 

 

Flags

 

 

 

 

 

 

 

 

 

 

 

 

E6AB

1

EP2FIFOBCH

Endpoint 2 slave FIFO

0

0

0

BC12

BC11

BC10

BC9

BC8

 

00000000

R

 

 

 

 

total byte count H

 

 

 

 

 

 

 

 

 

 

 

 

E6AC

1

EP2FIFOBCL

Endpoint 2 slave FIFO

BC7

BC6

BC5

BC4

BC3

BC2

BC1

BC0

 

00000000

R

 

 

 

 

total byte count L

 

 

 

 

 

 

 

 

 

 

 

 

E6AD

1

EP4FIFOBCH

Endpoint 4 slave FIFO

0

0

0

0

0

BC10

BC9

BC8

 

00000000

R

 

 

 

 

total byte count H

 

 

 

 

 

 

 

 

 

 

 

 

E6AE

1

EP4FIFOBCL

Endpoint 4 slave FIFO

BC7

BC6

BC5

BC4

BC3

BC2

BC1

BC0

 

00000000

R

 

 

 

 

total byte count L

 

 

 

 

 

 

 

 

 

 

 

 

E6AF

1

EP6FIFOBCH

Endpoint 6 slave FIFO

0

0

0

0

BC11

BC10

BC9

BC8

 

00000000

R

 

 

 

 

total byte count H

 

 

 

 

 

 

 

 

 

 

 

 

E6B0

1

EP6FIFOBCL

Endpoint 6 slave FIFO

BC7

BC6

BC5

BC4

BC3

BC2

BC1

BC0

 

00000000

R

 

 

 

 

total byte count L

 

 

 

 

 

 

 

 

 

 

 

 

E6B1

1

EP8FIFOBCH

Endpoint 8 slave FIFO

0

0

0

0

0

BC10

BC9

BC8

 

00000000

R

 

 

 

 

total byte count H

 

 

 

 

 

 

 

 

 

 

 

 

E6B2

1

EP8FIFOBCL

Endpoint 8 slave FIFO

BC7

BC6

BC5

BC4

BC3

BC2

BC1

BC0

 

00000000

R

 

 

 

 

total byte count L

 

 

 

 

 

 

 

 

 

 

 

 

E6B3

1

SUDPTRH

Setup Data Pointer high

A15

A14

A13

A12

A11

A10

A9

A8

 

xxxxxxxx

RW

 

 

 

 

address byte

 

 

 

 

 

 

 

 

 

 

 

 

E6B4

1

SUDPTRL

Setup Data Pointer low ad-

A7

A6

A5

A4

A3

A2

A1

0

 

xxxxxxx0

bbbbbbbr

 

 

 

 

dress byte

 

 

 

 

 

 

 

 

 

 

 

 

E6B5

1

SUDPTRCTL

Setup Data Pointer Auto

0

0

0

0

0

0

0

SDPAUTO

 

00000001

RW

 

 

 

 

Mode

 

 

 

 

 

 

 

 

 

 

 

 

 

2

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

E6B8

8

SET-UPDAT

8 bytes of setup data

D7

D6

D5

D4

D3

D2

D1

D0

 

xxxxxxxx

R

 

 

 

 

SET-UPDAT[0] =

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bmRequestType

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SET-UPDAT[1] =

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bmRequest

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SET-UPDAT[2:3] = wVal-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ue

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SET-UPDAT[4:5] = wInd-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ex

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SET-UPDAT[6:7] =

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

wLength

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIF

 

 

 

 

 

 

 

 

 

 

 

 

 

E6C0

1

GPIFWFSELECT

Waveform Selector

SINGLEWR1

SINGLEWR0

SINGLERD1

SINGLERD0

FIFOWR1

FIFOWR0

FIFORD1

FIFORD0

 

11100100

RW

 

E6C1

1

GPIFIDLECS

GPIF Done, GPIF IDLE

DONE

0

0

0

0

0

0

IDLEDRV

 

10000000

RW

 

 

 

 

drive mode

 

 

 

 

 

 

 

 

 

 

 

 

E6C2

1

GPIFIDLECTL

Inactive Bus, CTL states

0

0

CTL5

CTL4

CTL3

CTL2

CTL1

CTL0

 

11111111

RW

 

E6C3

1

GPIFCTLCFG

CTL Drive Type

TRICTL

0

CTL5

CTL4

CTL3

CTL2

CTL1

CTL0

 

00000000

RW

 

E6C4

1

GPIFADRH[7]

GPIF Address H

0

0

0

0

0

0

0

GPIFA8

 

00000000

RW

 

E6C5

1

GPIFADRL[7]

GPIF Address L

GPIFA7

GPIFA6

GPIFA5

GPIFA4

GPIFA3

GPIFA2

GPIFA1

GPIFA0

 

00000000

RW

 

 

 

FLOWSTATE

 

 

 

 

 

 

 

 

 

 

 

 

 

E6C6

1

FLOWSTATE

Flowstate Enable and

FSE

0

0

0

0

FS2

FS1

FS0

 

00000000

brrrrbbb

 

 

 

 

Selector

 

 

 

 

 

 

 

 

 

 

 

 

E6C7

1

FLOWLOGIC

Flowstate Logic

LFUNC1

LFUNC0

TERMA2

TERMA1

TERMA0

TERMB2

TERMB1

TERMB0

 

00000000

RW

 

E6C8

1

FLOWEQ0CTL

CTL-Pin States in

CTL0E3

CTL0E2

CTL0E1/

CTL0E0/

CTL3

CTL2

CTL1

CTL0

 

00000000

RW

 

 

 

 

Flowstate

 

 

CTL5

CTL4

 

 

 

 

 

 

 

 

 

 

 

(when Logic = 0)

 

 

 

 

 

 

 

 

 

 

 

 

E6C9

1

FLOWEQ1CTL

CTL-Pin States in Flow-

CTL0E3

CTL0E2

CTL0E1/

CTL0E0/

CTL3

CTL2

CTL1

CTL0

 

00000000

RW

 

 

 

 

state (when Logic = 1)

 

 

CTL5

CTL4

 

 

 

 

 

 

 

 

E6CA

1

FLOWHOLDOFF

Holdoff Configuration

HOPERIOD3

HOPERIOD2

HOPERIOD1

HOPERIOD

HOSTATE

HOCTL2

HOCTL1

HOCTL0

 

00010010

RW

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

E6CB

1

FLOWSTB

Flowstate Strobe

SLAVE

RDYASYNC

CTLTOGL

SUSTAIN

0

MSTB2

MSTB1

MSTB0

 

00100000

RW

 

 

 

 

Configuration

 

 

 

 

 

 

 

 

 

 

 

 

E6CC

1

FLOWSTBEDGE

Flowstate Rising/Falling

0

0

0

0

0

0

FALLING

RISING

 

00000001

rrrrrrbb

 

 

 

 

Edge Configuration

 

 

 

 

 

 

 

 

 

 

 

Document #: 001-04247 Rev. *D

 

 

 

 

 

 

 

 

Page 21 of 33

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Contents Block Diagram CY7C68033/CY7C68034 Silicon FeaturesCY7C68034 Only Silicon Features CY7C68033 Only Silicon FeaturesDefault Nand Firmware Features OverviewApplications Functional Overview USB Signaling SpeedClock Frequency Special Function RegistersPSW ACC Exif INT2CLR IOE SBUF1 IOA IOB IOC IODMpage INT4CLR OEA OEB DPL1 OEC DPH1 OED DPS OEEBus-powered Applications Default Silicon ID Values Default VID/PID/DIDDefault Silicon ID Values ReNumerationUSB Interrupt Table for INT2 INT2 USB InterruptsPriority INT2VEC Value Source FIFO/GPIF Interrupt INT4Reset Pin Reset and WakeupReset Timing Values Condition Program/Data RAMRegister Addresses Endpoint RAM Default Full-Speed Alternate Settings2Default High-Speed Alternate Settings2 External Fifo InterfaceGpif Autopointer Access ECC Generation5I2C Controller Pin Assignments Feature programmable polarityCY7C68033/CY7C68034 Pin Default Description Name NX2LP-Flex Pin Descriptions 56 QFN Default PinNand TypePort a Port D Port BGround Power and GroundNX2LP-Flex Register Summary Register SummaryRegister can only be reset, it cannot be set Nakirq EP0CS E6CD Flowstbperiod SEL Operating Conditions Absolute Maximum RatingsDC Characteristics AC Electrical CharacteristicsUSB Transceiver Slave Fifo Asynchronous Write Slave Fifo Asynchronous ReadSlave Fifo Output Enable Slave Fifo Asynchronous Packet End StrobeSlave Fifo Address to Flags/Data RD/WR/PKTEND to FIFOADR10 Hold Time Sequence Diagram FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous AddressSlave Fifo Asynchronous Write Sequence and Timing Diagram13 Sequence Diagram of a Single and Burst Asynchronous WriteOrdering Information Package DiagramQuad Flat Package No Leads QFN Package Design Notes PCB Layout Recommendations16Plot of the Solder Mask White Area Issue Date Orig. Description of Change Document HistoryREV ECN no