Cypress CY7C68033 manual Slave Fifo Asynchronous Address, FIFOADR10 to SLRD/SLWR/PKTEND Setup Time

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CY7C68033/CY7C68034

Slave FIFO Asynchronous Address

Figure 16. Slave FIFO Asynchronous Address Timing Diagram[13]

SLCS/FIFOADR [1:0]

tSFA

SLRD/SLWR/PKTEND

tFAH

Table 16.Slave FIFO Asynchronous Address Parameters[15]

Parameter	Description	Min.	Max.	Unit
tSFA	FIFOADR[1:0] to SLRD/SLWR/PKTEND Setup Time	10		ns
tFAH	RD/WR/PKTEND to FIFOADR[1:0] Hold Time	10		ns

Sequence Diagram

Sequence Diagram of a Single and Burst Asynchronous Read

Figure 17. Slave FIFO Asynchronous Read Sequence and Timing Diagram[13]

t

t

t

SFA

tFAH

SFA

FAH

FIFOADR

t=0

tRDpwl

tRDpwh

tRDpwl

tRDpwh

tRDpwl

tRDpwh

tRDpwl tRDpwh

T=0

SLRD

t=2

t=3

T=2

T=3

T=4

T=5

T=6

SLCS

tXFLG

tXFLG

FLAGS

tXFD

tXFD

tXFD

t

XFD

DATA

Data (X)

N

N

N+1

N+2

N+3

Driven

t

t

OEoff

tOEon

tOEoff

OEon

SLOE

t=1

t=4

T=1

T=7

Figure 18. Slave FIFO Asynchronous Read Sequence of Events Diagram

FIFO POINTER

SLOE

SLRD

SLRD

SLOE

SLOE

SLRD

SLRD

SLRD

SLRD

SLOE

N

N

N

N+1

N+1

N+1

N+1

N+2

N+2

N+3

N+3

FIFO DATA BUS

Not Driven			Driven: X			N
Not Driven			Driven: X			N

N Not Driven N N+1 N+1 N+2 N+2 Not Driven

Document #: 001-04247 Rev. *D

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Contents CY7C68033/CY7C68034 Silicon Features Block DiagramCY7C68034 Only Silicon Features CY7C68033 Only Silicon FeaturesOverview Default Nand Firmware FeaturesApplications USB Signaling Speed Functional OverviewClock Frequency Special Function RegistersIOA IOB IOC IOD PSW ACC Exif INT2CLR IOE SBUF1Mpage INT4CLR OEA OEB DPL1 OEC DPH1 OED DPS OEEDefault Silicon ID Values Default VID/PID/DID Bus-powered ApplicationsDefault Silicon ID Values ReNumerationINT2 USB Interrupts USB Interrupt Table for INT2Priority INT2VEC Value Source FIFO/GPIF Interrupt INT4Reset and Wakeup Reset PinProgram/Data RAM Reset Timing Values ConditionRegister Addresses Default Full-Speed Alternate Settings2 Endpoint RAMExternal Fifo Interface Default High-Speed Alternate Settings2Gpif ECC Generation5 Autopointer AccessI2C Controller Feature programmable polarity Pin AssignmentsCY7C68033/CY7C68034 NX2LP-Flex Pin Descriptions 56 QFN Default Pin Pin Default Description NameNand TypePort a Port B Port DPower and Ground GroundRegister Summary NX2LP-Flex Register SummaryRegister can only be reset, it cannot be set Nakirq EP0CS E6CD Flowstbperiod SEL Absolute Maximum Ratings Operating ConditionsAC Electrical Characteristics DC CharacteristicsUSB Transceiver Slave Fifo Asynchronous Read Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Output EnableSlave Fifo Address to Flags/Data FIFOADR10 to SLRD/SLWR/PKTEND Setup Time RD/WR/PKTEND to FIFOADR10 Hold Time Sequence DiagramSequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous AddressSequence Diagram of a Single and Burst Asynchronous Write Slave Fifo Asynchronous Write Sequence and Timing Diagram13Package Diagram Ordering InformationPCB Layout Recommendations16 Quad Flat Package No Leads QFN Package Design NotesPlot of the Solder Mask White Area Document History Issue Date Orig. Description of ChangeREV ECN no