Cypress CY7C68033 INT2 USB Interrupts, USB Interrupt Table for INT2, FIFO/GPIF Interrupt INT4

Page 6

CY7C68033/CY7C68034

Table 3. INT2 USB Interrupts

USB INTERRUPT TABLE FOR INT2

Priority

INT2VEC Value

Source

Notes

1

0x500

SUDAV

Setup Data Available

 

 

 

 

2

0x504

SOF

Start of Frame (or microframe)

 

 

 

 

3

0x508

SUTOK

Setup Token Received

 

 

 

 

4

0x50C

SUSPEND

USB Suspend request

 

 

 

 

5

0x510

USB RESET

Bus reset

 

 

 

 

6

0x514

HISPEED

Entered high speed operation

 

 

 

 

7

0x518

EP0ACK

NX2LP ACK’d the CONTROL Handshake

 

 

 

 

8

0x51C

 

Reserved

 

 

 

 

9

0x520

EP0-IN

EP0-IN ready to be loaded with data

 

 

 

 

10

0x524

EP0-OUT

EP0-OUT has USB data

 

 

 

 

11

0x528

EP1-IN

EP1-IN ready to be loaded with data

 

 

 

 

12

0x52C

EP1-OUT

EP1-OUT has USB data

 

 

 

 

13

0x530

EP2

IN: buffer available. OUT: buffer has data

 

 

 

 

14

0x534

EP4

IN: buffer available. OUT: buffer has data

 

 

 

 

15

0x538

EP6

IN: buffer available. OUT: buffer has data

 

 

 

 

16

0x53C

EP8

IN: buffer available. OUT: buffer has data

 

 

 

 

17

0x540

IBN

IN-Bulk-NAK (any IN endpoint)

 

 

 

 

18

0x544

 

Reserved

 

 

 

 

19

0x548

EP0PING

EP0 OUT was Pinged and it NAK’d

 

 

 

 

20

0x54C

EP1PING

EP1 OUT was Pinged and it NAK’d

 

 

 

 

21

0x550

EP2PING

EP2 OUT was Pinged and it NAK’d

 

 

 

 

22

0x554

EP4PING

EP4 OUT was Pinged and it NAK’d

 

 

 

 

23

0x558

EP6PING

EP6 OUT was Pinged and it NAK’d

 

 

 

 

24

0x55C

EP8PING

EP8 OUT was Pinged and it NAK’d

 

 

 

 

25

0x560

ERRLIMIT

Bus errors exceeded the programmed limit

 

 

 

 

26

0x564

 

Reserved

 

 

 

 

27

0x568

 

Reserved

 

 

 

 

28

0x56C

 

Reserved

 

 

 

 

29

0x570

EP2ISOERR

ISO EP2 OUT PID sequence error

 

 

 

 

30

0x574

EP4ISOERR

ISO EP4 OUT PID sequence error

 

 

 

 

31

0x578

EP6ISOERR

ISO EP6 OUT PID sequence error

 

 

 

 

32

0x57C

EP8ISOERR

ISO EP8 OUT PID sequence error

 

 

 

 

If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the NX2LP-Flex substitutes its INT2VEC byte. Therefore, if the high byte (‘page’) of a jump-table address is preloaded at location 0x544, the automatically-inserted INT2VEC byte at 0x545 will direct the jump to the correct address out of the 27 addresses within the page.

FIFO/GPIF Interrupt (INT4)

Just as the USB Interrupt is shared among 27 individual USB-interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. Table 4 shows the priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources.

Document #: 001-04247 Rev. *D

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Contents CY7C68034 Only Silicon Features CY7C68033/CY7C68034 Silicon FeaturesBlock Diagram CY7C68033 Only Silicon FeaturesDefault Nand Firmware Features OverviewApplications Clock Frequency USB Signaling SpeedFunctional Overview Special Function RegistersMpage INT4CLR OEA IOA IOB IOC IODPSW ACC Exif INT2CLR IOE SBUF1 OEB DPL1 OEC DPH1 OED DPS OEEDefault Silicon ID Values Default Silicon ID Values Default VID/PID/DIDBus-powered Applications ReNumerationPriority INT2VEC Value Source INT2 USB InterruptsUSB Interrupt Table for INT2 FIFO/GPIF Interrupt INT4Reset and Wakeup Reset PinReset Timing Values Condition Program/Data RAMRegister Addresses Default Full-Speed Alternate Settings2 Endpoint RAMDefault High-Speed Alternate Settings2 External Fifo InterfaceGpif Autopointer Access ECC Generation5I2C Controller Feature programmable polarity Pin AssignmentsCY7C68033/CY7C68034 Nand NX2LP-Flex Pin Descriptions 56 QFN Default PinPin Default Description Name TypePort a Port B Port DPower and Ground GroundRegister Summary NX2LP-Flex Register SummaryRegister can only be reset, it cannot be set Nakirq EP0CS E6CD Flowstbperiod SEL Absolute Maximum Ratings Operating ConditionsDC Characteristics AC Electrical CharacteristicsUSB Transceiver Slave Fifo Asynchronous Read Slave Fifo Asynchronous WriteSlave Fifo Output Enable Slave Fifo Asynchronous Packet End StrobeSlave Fifo Address to Flags/Data Sequence Diagram of a Single and Burst Asynchronous Read FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeRD/WR/PKTEND to FIFOADR10 Hold Time Sequence Diagram Slave Fifo Asynchronous AddressSequence Diagram of a Single and Burst Asynchronous Write Slave Fifo Asynchronous Write Sequence and Timing Diagram13Package Diagram Ordering InformationPCB Layout Recommendations16 Quad Flat Package No Leads QFN Package Design NotesPlot of the Solder Mask White Area Issue Date Orig. Description of Change Document HistoryREV ECN no