A2CR24. The A2R113-A2R114 voltage divider sets the maximum CP voltage to + 1.5Vdc and assures that the diode with the lower control voltage will be forward biased when its control voltage is less than + 1.5Vdc. As an illustration of CV-CC selection, suppose the unit is in CV operation and diode A2CR24 is forward biased by a low CV CONTRL Voltage: Then CV sets CP to less than + 1.5Vdc.
CV keeps diode A2CR19 reverse biased and prevents CC control until the CC CONTROL Voltage is even lower.
The lower of the control voltages varies between about--0.5Vdc and + 1.0Vdc regulating the unit's output. The higher control voltage has no effect on the output and increases in response to the error voltage in its circuit. When higher, the CC CONTROL Voltage limits at about 6Vdc. When higher, the CV CONTROL Voltage increases only slightly. In CV or CC mode CP remains one diode-drop more than the lower control voltage and varies from about 0.0 to + 1.5Vdc. In UNREGULATED mode CP is +1.5Vdc and both control voltages are more than about + 1.0Vdc.
Initial-Ramp Circuit
The Control Voltage and Ramp Voltage waveforms in Figure 4-4 show that there is a time delay between when the control voltage is exceeded and when the PFETs turn off. This cumulative circuit delay would cause the PFETs to deliver power even when no power is requested by the control circuits. To eliminate the delay, the Initial-Ramp Circuit adds a ramp voltage to the Ip-RAMP VOLTAGE at the input to the Control Voltage Comparator. The added ramp voltage starts with the 20KHz clock pulse and causes the combined-ramp voltage to exceed the control voltage earlier thereby essentially eliminating the PFET turn-off delay. A two-stage RC integrating network consisting of resistors A2R116 and A2R117 and capacitors A2C59 and A2C61 creates the Initial-Ramp by shaping the 20KHz clock pulses.
Pulse-Width Modulator (PWM)
The PWM generates 20KHz repetition-rate pulses which vary in length according to the unit's output requirements. The pulses start 1.5∝ after each 20KHz clock pulse and turn off when any of these four inputs go low. The output of the Control-Voltage Comparator (CONTROL V LIMIT), the output of the Power-Limit Comparator (POWER LIMIT), the 20KHz clock pulse (50%-DUTY-CYCLE LIMIT), or the output of the Inhibit Gate A2U19A (MASTER ENABLE). As discussed earlier, the PFETs turn on during, and turn off at the trailing edges of PWM output pulses.
The PWM generates pulses as follows: A 20KHz clock pulse holds the 1.5∝ Delay Flip-flop A2U13B reset; 1.5∝ after the trailing edge of the 20KHz pulse, the next pulse from the 320KHz Clock oscillator clocks the output of A2U13B high, and this initiates the PWM pulse from PWM Flip-flop A2U13A. When one of the above four inputs to AND-gate A2U19B goes low. A2U19B resets A2U13A, and the PWM pulse turns off.
Bias Voltage Detector
The Bias Voltage Detector prevents spurious operation which might occur at power-on of the unit if circuits tried to operate before the + 5Vdc bias voltage is at the clock, PWM, and logic circuits. After power-on, as the output of the + 5Vdc bias supply rises from 0Vdc through about 1Vdc, three transistor switches in the Bias Voltage Detector turn on. They inhibit the Relay Driver and the on-Pulse Driver, and they create the power-clear signal, PCLR2. The transistors inhibit the circuits and hold PCLR2 low until the unregulated input to the +5Vdc bias supply is greater than about 11Vdc, an input voltage sufficient to assure + 5Vdc bias output. PCLR2 resets the OVP at turn-on, and Option 002 uses PCLR2 in creating its DROPOUT, OVERVOLTAGE, and POWER-ON RESET outputs.
AC-Surge Dropout Detector
Dropout Detector protects the unit from damage from ac mains voltage surges and dropouts by shutting down the unit when there is either a 40% overvoltage or a 20 ms voltage interruption in the ac mains voltage. The detector shuts down the unit