Xilinx UG518 manual Features, SP601 Evaluation Board

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Chapter 1: SP601 Evaluation Board

Features

The SP601 board provides the following features:

•1. Spartan-6XC6SLX16-2CSG324 FPGA

•2. 128 MB DDR2 Component Memory

•3. SPI x4 Flash

•4. Linear Flash BPI

•5. 10/100/1000 Tri-Speed Ethernet PHY

•7. IIC Bus

♦8Kb NV memory

♦External access 2-pin header

♦VITA 57.1 FMC-LPC connector

•8. Clock Generation

♦Oscillator (Differential)

♦Oscillator Socket (Single-Ended, 2.5V or 3.3V)

•SMA Connectors (Differential)

•9. VITA 57.1 FMC-LPC Connector

•10. Status LEDs

♦FPGA_AWAKE

♦INIT

♦DONE

•13. User I/O

♦User LEDs

♦User DIP switch

♦User pushbuttons

♦GPIO male pin header

•14. FPGA_PROG_B Pushbutton Switch

•Configuration Options

♦3. SPI x4 Flash (both onboard and off-board)

♦4. Linear Flash BPI

♦JTAG Configuration

•Power Management - AC Adapter and 5V Input Power Jack/Switch, Onboard Power Supplies

10	www.xilinx.com	SP601 Hardware User Guide
		UG518 (v1.1) August 19, 2009

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Contents SP601 Hardware User Guide UG518 v1.1 August 19, 2009 optionalSP601 Hardware User Guide Revision History Date Version RevisionSP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 About This Guide Guide ContentsAdditional Resources Conventions Preface About This Guide Online DocumentMeaning or Use Example Overview SP601 Evaluation BoardAdditional Information Features SP601 Evaluation BoardRelated Xilinx Documents Block DiagramRelated Xilinx Documents Feature SP601 FeaturesDetailed Description Detailed Description SP601 Features Cont’d NumberSpartan-6 XC6SLX16-2CSG324 Fpga 2I/O Voltage Rail of Fpga BanksMB DDR2 Component Memory 5DDR2 Component Memory Connections Schematic Netname Memory U2Name 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins SPI x4 Flash 6J12 SPI Flash Programming HeaderSchematic Netname Pin #Linear Flash BPI 8UCF Location Constraints for BPI Flash ConnectionsFLASHA6 10UCF Location Constraints for BPI Flash Connections 10/100/1000 Tri-Speed Ethernet PHY 8PHY Configuration PinsSchematic Netname U3 M88E111 Pin Bit2 Bit1 Bit0Schematic Netname U3 M88E111 SP601 Evaluation Board 9PHY Connections Cont’dUSB-to-UART Bridge CP2103GM ConnectionsIIC Bus 13IIC Bus TopologyClock Generation 14UCF Location Constraints for IIC ConnectionsVita 57.1 FMC-LPC Connector 16UCF Location Constraints for Oscillator Socket Connections13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Reference Signal Name Color Label Description Status LEDsSuspend Mode I/O Fpga Awake LED and Suspend JumperFpga Init and Done LEDs Controlled LEDReference Signal Name Color Label Fpga Pin User I/OUser DIP switch Reference Signal Name Color Label Fpga Pin DesignatorUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O AC Adapter and 5V Input Power Jack/Switch Power ManagementFpgaprogb Pushbutton Switch Onboard Power SuppliesPower Management 22Estimated Current Draw Rail Estimated Current aConfiguration Options Jtag ConfigurationConfiguration Options 32VITA 57.1 FMC Jtag Bypass JumperSP601 Evaluation Board References Appendix a References Table B-1Default Jumper and Switch Settings Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Table C-1VITA 57.1 FMC LPC Connections Vita 57.1 FMC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn