Xilinx UG518 manual User I/O, Reference Signal Name Color Label Fpga Pin

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Detailed Description

13. User I/O

The SP601 provides the following user and general purpose I/O capabilities:

•User LEDs

•User DIP switch

•Pushbutton switches

•CPU Reset pushbutton switch

•GPIO male pin header

Note: All GPIO location constraints are collected in one partial UCF in Figure 1-27.

User LEDs

The SP601 provides four active high, green LEDs, as described in Figure 1-23and

Table 1-17.

GPIO LED 3

GPIO LED 2
GPIO LED 1
GPIO LED 0
	2			2		2				2
LED-GRN	DS11	LED-GRN		DS12	LED-GRN		DS13	LED-GRN		DS14
-S	1	-S		1	-S	1		-S		1
MT		MT			MT			MT
1	R91		1	R92		1	R93		1	R94
	R91			R92			R93			R94
	27.4			27.4			27.4			27.4
2	1%		2	1%		2	1%		2	1%
2	1/16W		2	1/16W		2	1/16W		2	1/16W
	1/16W			1/16W			1/16W			1/16W
									UG518_23_070809
	Figure 1-23: User LEDs

Table 1-17: User LEDs

	Reference	Signal Name	Color	Label	FPGA Pin
	Designator	Signal Name	Color	Label	FPGA Pin
	Designator

	DS11	GPIO_LED_0	Green		E13

	DS12	GPIO_LED_1	Green		C14

SP601 Hardware User Guide

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UG518 (v1.1) August 19, 2009

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Contents UG518 v1.1 August 19, 2009 optional SP601 Hardware User GuideSP601 Hardware User Guide Date Version Revision Revision HistorySP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Additional Resources Conventions Guide ContentsAbout This Guide Meaning or Use Example Online DocumentPreface About This Guide Additional Information SP601 Evaluation BoardOverview SP601 Evaluation Board FeaturesRelated Xilinx Documents Block DiagramRelated Xilinx Documents Detailed Description SP601 FeaturesFeature 2I/O Voltage Rail of Fpga Banks SP601 Features Cont’d NumberSpartan-6 XC6SLX16-2CSG324 Fpga Detailed DescriptionMB DDR2 Component Memory Name Schematic Netname Memory U25DDR2 Component Memory Connections 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins 6J12 SPI Flash Programming Header SPI x4 FlashPin # Schematic Netname8UCF Location Constraints for BPI Flash Connections Linear Flash BPIFLASHA6 10UCF Location Constraints for BPI Flash Connections Bit2 Bit1 Bit0 8PHY Configuration PinsSchematic Netname U3 M88E111 Pin 10/100/1000 Tri-Speed Ethernet PHYSP601 Evaluation Board 9PHY Connections Cont’d Schematic Netname U3 M88E111CP2103GM Connections USB-to-UART Bridge13IIC Bus Topology IIC Bus14UCF Location Constraints for IIC Connections Clock Generation16UCF Location Constraints for Oscillator Socket Connections Vita 57.1 FMC-LPC Connector13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Status LEDs Reference Signal Name Color Label DescriptionFpga Awake LED and Suspend Jumper Suspend Mode I/OControlled LED Fpga Init and Done LEDsUser I/O Reference Signal Name Color Label Fpga PinReference Signal Name Color Label Fpga Pin Designator User DIP switchUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Onboard Power Supplies Power ManagementFpgaprogb Pushbutton Switch AC Adapter and 5V Input Power Jack/Switch22Estimated Current Draw Rail Estimated Current a Power ManagementJtag Configuration Configuration Options32VITA 57.1 FMC Jtag Bypass Jumper Configuration OptionsSP601 Evaluation Board References Appendix a References Type/Function Default Default Jumper and Switch SettingsTable B-1Default Jumper and Switch Settings Appendix B Default Jumper and Switch Settings LPC Pin Vita 57.1 FMC ConnectionsTable C-1VITA 57.1 FMC LPC Connections FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn