Xilinx UG518 manual Status LEDs, Reference Signal Name Color Label Description

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Chapter 1: SP601 Evaluation Board

10. Status LEDs

Table 1-14defines the status LEDs.

Table 1-14: Status LEDs

	Reference	Signal Name	Color	Label	Description
	Designator	Signal Name	Color	Label	Description
	Designator

	DS1	FMC_PWR_GOOD_		PWR	Indicates power available for
		FMC_PWR_GOOD_	Green	PWR	VITA 57.1 FMC expansion
		FLASH_RST_B	Green	GOOD	VITA 57.1 FMC expansion
		FLASH_RST_B		GOOD	connector.
					connector.

	DS2	PHY_LED_LINK10	Green	10

	DS3	PHY_LED_LINK100	Green	100

	DS4	PHY_LED_LINK100	Green	1000
		0	Green	1000
		0

	DS5	PHY_LED_DUPLEX	Green	DUP

	DS6	PHY_LED_RX	Green	RX

	DS7	PHY_LED_TX	Green	TX

	DS8	FPGA_AWAKE	Green	AWAKE

	DS9				Illuminates to indicate the
		FPGA_DONE	Green	DONE	status of the DONE pin when
		FPGA_DONE	Green	DONE	the FPGA is successfully
					the FPGA is successfully
					configured.

	DS10				Illuminates after power-up to
					indicate that the FPGA has
		FPGA_INIT	Red	INIT	successfully powered up and
					completed its internal power-
					on process.

	DS15	VCC5	Green		Illuminates when 5V supply is
		VCC5	Green		applied.
					applied.

	DS16	LED_GRN,	Green/	STATUS	USB to JTAG logic.
		LED_RED	Red	STATUS	USB to JTAG logic.
		LED_RED	Red

	DS17	LTC_PWR_GOOD	Green		Illuminates to indicate that the
		LTC_PWR_GOOD	Green		board power is good.
					board power is good.

32	www.xilinx.com	SP601 Hardware User Guide
		UG518 (v1.1) August 19, 2009

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Contents SP601 Hardware User Guide UG518 v1.1 August 19, 2009 optionalSP601 Hardware User Guide Revision History Date Version RevisionSP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Additional Resources Conventions Guide ContentsAbout This Guide Meaning or Use Example Online DocumentPreface About This Guide Additional Information SP601 Evaluation BoardOverview Features SP601 Evaluation BoardRelated Xilinx Documents Block DiagramRelated Xilinx Documents Detailed Description SP601 FeaturesFeature SP601 Features Cont’d Number Spartan-6 XC6SLX16-2CSG324 FpgaDetailed Description 2I/O Voltage Rail of Fpga BanksMB DDR2 Component Memory Name Schematic Netname Memory U25DDR2 Component Memory Connections 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins SPI x4 Flash 6J12 SPI Flash Programming HeaderSchematic Netname Pin #Linear Flash BPI 8UCF Location Constraints for BPI Flash ConnectionsFLASHA6 10UCF Location Constraints for BPI Flash Connections 8PHY Configuration Pins Schematic Netname U3 M88E111 Pin10/100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0Schematic Netname U3 M88E111 SP601 Evaluation Board 9PHY Connections Cont’dUSB-to-UART Bridge CP2103GM ConnectionsIIC Bus 13IIC Bus TopologyClock Generation 14UCF Location Constraints for IIC ConnectionsVita 57.1 FMC-LPC Connector 16UCF Location Constraints for Oscillator Socket Connections13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Reference Signal Name Color Label Description Status LEDsSuspend Mode I/O Fpga Awake LED and Suspend JumperFpga Init and Done LEDs Controlled LEDReference Signal Name Color Label Fpga Pin User I/OUser DIP switch Reference Signal Name Color Label Fpga Pin DesignatorUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Power Management Fpgaprogb Pushbutton SwitchAC Adapter and 5V Input Power Jack/Switch Onboard Power SuppliesPower Management 22Estimated Current Draw Rail Estimated Current aConfiguration Options Jtag ConfigurationConfiguration Options 32VITA 57.1 FMC Jtag Bypass JumperSP601 Evaluation Board References Appendix a References Type/Function Default Default Jumper and Switch SettingsTable B-1Default Jumper and Switch Settings Appendix B Default Jumper and Switch Settings LPC Pin Vita 57.1 FMC ConnectionsTable C-1VITA 57.1 FMC LPC Connections FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn