Xilinx UG518 manual Vita 57.1 FMC Connections, Table C-1VITA 57.1 FMC LPC Connections, LPC Pin

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Appendix C

VITA 57.1 FMC Connections

Table C-1shows the VITA 57.1 FMC LPC connections.

Table C-1:VITA 57.1 FMC LPC Connections

J1 FMC	Schematic Netname	U1 FPGA		J1 FMC	Schematic Netname	U1 FPGA
LPC Pin	Schematic Netname	Pin		LPC Pin	Schematic Netname	Pin
LPC Pin		Pin		LPC Pin		Pin

C10	FMC_LA06_P	D12		D1	FMC_PWR_GOOD_FLASH_RST_B	B3

C11	FMC_LA06_N	C12		D8	FMC_LA01_CC_P	D11

C14	FMC_LA10_P	D8		D9	FMC_LA01_CC_N	C11

C15	FMC_LA10_N	C8		D11	FMC_LA05_P	B14

C18	FMC_LA14_P	B2		D12	FMC_LA05_N	A14

C19	FMC_LA14_N	A2		D14	FMC_LA09_P	G11

C22	FMC_LA18_CC_P	R10		D15	FMC_LA09_N	F10

C23	FMC_LA18_CC_N	T10		D17	FMC_LA13_P	B11

C26	FMC_LA27_P	R11		D18	FMC_LA13_N	A11

C27	FMC_LA27_N	T11		D20	FMC_LA17_CC_P	R8

C30	IIC_SCL_MAIN	P11		D21	FMC_LA17_CC_N	T8

C31	IIC_SDA_MAIN	N10		D23	FMC_LA23_P	N5

				D24	FMC_LA23_N	P6

				D26	FMC_LA26_P	U7

				D27	FMC_LA26_N	V7


G2	FMC_CLK1_M2C_P	T9		H2	FMC_PRSNT_M2C_L	U13

G3	FMC_CLK1_M2C_N	V9		H4	FMC_CLK0_M2C_P	C10

G6	FMC_LA00_CC_P	D9		H5	FMC_CLK0_M2C_N	A10

G7	FMC_LA00_CC_N	C9		H7	FMC_LA02_P	C15

G9	FMC_LA03_P	C13		H8	FMC_LA02_N	A15

G10	FMC_LA03_N	A13		H10	FMC_LA04_P	B16

G12	FMC_LA08_P	F11		H11	FMC_LA04_N	A16

SP601 Hardware User Guide

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UG518 (v1.1) August 19, 2009

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Contents UG518 v1.1 August 19, 2009 optional SP601 Hardware User GuideSP601 Hardware User Guide Date Version Revision Revision HistorySP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 About This Guide Guide ContentsAdditional Resources Conventions Preface About This Guide Online DocumentMeaning or Use Example Overview SP601 Evaluation BoardAdditional Information SP601 Evaluation Board FeaturesRelated Xilinx Documents Block DiagramRelated Xilinx Documents Feature SP601 FeaturesDetailed Description Spartan-6 XC6SLX16-2CSG324 Fpga SP601 Features Cont’d NumberDetailed Description 2I/O Voltage Rail of Fpga BanksMB DDR2 Component Memory 5DDR2 Component Memory Connections Schematic Netname Memory U2Name 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins 6J12 SPI Flash Programming Header SPI x4 FlashPin # Schematic Netname8UCF Location Constraints for BPI Flash Connections Linear Flash BPIFLASHA6 10UCF Location Constraints for BPI Flash Connections Schematic Netname U3 M88E111 Pin 8PHY Configuration Pins10/100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0SP601 Evaluation Board 9PHY Connections Cont’d Schematic Netname U3 M88E111CP2103GM Connections USB-to-UART Bridge13IIC Bus Topology IIC Bus14UCF Location Constraints for IIC Connections Clock Generation16UCF Location Constraints for Oscillator Socket Connections Vita 57.1 FMC-LPC Connector13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Status LEDs Reference Signal Name Color Label DescriptionFpga Awake LED and Suspend Jumper Suspend Mode I/OControlled LED Fpga Init and Done LEDsUser I/O Reference Signal Name Color Label Fpga PinReference Signal Name Color Label Fpga Pin Designator User DIP switchUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Fpgaprogb Pushbutton Switch Power ManagementAC Adapter and 5V Input Power Jack/Switch Onboard Power Supplies22Estimated Current Draw Rail Estimated Current a Power ManagementJtag Configuration Configuration Options32VITA 57.1 FMC Jtag Bypass Jumper Configuration OptionsSP601 Evaluation Board References Appendix a References Table B-1Default Jumper and Switch Settings Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Table C-1VITA 57.1 FMC LPC Connections Vita 57.1 FMC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn