Xilinx UG518 manual SP601 Master UCF

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Appendix D

SP601 Master UCF

The UCF template is provided for designs that target the SP601. Net names provided in the constraints below correlate with net names on the SP601 rev. C schematic. On identifying the appropriate pins, the net names below should be replaced with net names in the user RTL. See the Constraints Guide for more information.

NET "CPU_RESET" NET "DDR2_A0" NET "DDR2_A1" NET "DDR2_A2" NET "DDR2_A3" NET "DDR2_A4" NET "DDR2_A5" NET "DDR2_A6" NET "DDR2_A7" NET "DDR2_A8" NET "DDR2_A9" NET "DDR2_A10" NET "DDR2_A11" NET "DDR2_A12" NET "DDR2_BA0" NET "DDR2_BA1" NET "DDR2_BA2" NET "DDR2_CAS_B" NET "DDR2_CKE" NET "DDR2_CLK_N" NET "DDR2_CLK_P" NET "DDR2_DQ0" NET "DDR2_DQ1" NET "DDR2_DQ2" NET "DDR2_DQ3" NET "DDR2_DQ4" NET "DDR2_DQ5" NET "DDR2_DQ6" NET "DDR2_DQ7" NET "DDR2_DQ8" NET "DDR2_DQ9" NET "DDR2_DQ10" NET "DDR2_DQ11" NET "DDR2_DQ12" NET "DDR2_DQ13" NET "DDR2_DQ14" NET "DDR2_DQ15" NET "DDR2_LDM" NET "DDR2_LDQS_N"

LOC = "N4"; LOC = "J7"; LOC = "J6"; LOC = "H5"; LOC = "L7"; LOC = "F3"; LOC = "H4"; LOC = "H3"; LOC = "H6"; LOC = "D2"; LOC = "D1"; LOC = "F4"; LOC = "D3"; LOC = "G6"; LOC = "F2"; LOC = "F1"; LOC = "E1"; LOC = "K5"; LOC = "H7"; LOC = "G1"; LOC = "G3"; LOC = "L2"; LOC = "L1"; LOC = "K2"; LOC = "K1"; LOC = "H2"; LOC = "H1"; LOC = "J3"; LOC = "J1"; LOC = "M3"; LOC = "M1"; LOC = "N2"; LOC = "N1"; LOC = "T2"; LOC = "T1"; LOC = "U2"; LOC = "U1"; LOC = "K3"; LOC = "L3";

SP601 Hardware User Guide

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UG518 (v1.1) August 19, 2009

Image 51

Contents UG518 v1.1 August 19, 2009 optional SP601 Hardware User GuideSP601 Hardware User Guide Date Version Revision Revision HistorySP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Guide Contents About This GuideAdditional Resources Conventions Online Document Preface About This GuideMeaning or Use Example SP601 Evaluation Board OverviewAdditional Information SP601 Evaluation Board FeaturesBlock Diagram Related Xilinx DocumentsRelated Xilinx Documents SP601 Features FeatureDetailed Description 2I/O Voltage Rail of Fpga Banks SP601 Features Cont’d NumberSpartan-6 XC6SLX16-2CSG324 Fpga Detailed DescriptionMB DDR2 Component Memory Schematic Netname Memory U2 5DDR2 Component Memory ConnectionsName 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins 6J12 SPI Flash Programming Header SPI x4 FlashPin # Schematic Netname8UCF Location Constraints for BPI Flash Connections Linear Flash BPIFLASHA6 10UCF Location Constraints for BPI Flash Connections Bit2 Bit1 Bit0 8PHY Configuration PinsSchematic Netname U3 M88E111 Pin 10/100/1000 Tri-Speed Ethernet PHYSP601 Evaluation Board 9PHY Connections Cont’d Schematic Netname U3 M88E111CP2103GM Connections USB-to-UART Bridge13IIC Bus Topology IIC Bus14UCF Location Constraints for IIC Connections Clock Generation16UCF Location Constraints for Oscillator Socket Connections Vita 57.1 FMC-LPC Connector13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Status LEDs Reference Signal Name Color Label DescriptionFpga Awake LED and Suspend Jumper Suspend Mode I/OControlled LED Fpga Init and Done LEDsUser I/O Reference Signal Name Color Label Fpga PinReference Signal Name Color Label Fpga Pin Designator User DIP switchUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Onboard Power Supplies Power ManagementFpgaprogb Pushbutton Switch AC Adapter and 5V Input Power Jack/Switch22Estimated Current Draw Rail Estimated Current a Power ManagementJtag Configuration Configuration Options32VITA 57.1 FMC Jtag Bypass Jumper Configuration OptionsSP601 Evaluation Board References Appendix a References Default Jumper and Switch Settings Table B-1Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Vita 57.1 FMC Connections Table C-1VITA 57.1 FMC LPC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn