Xilinx UG518 manual Fpga Awake LED and Suspend Jumper, Suspend Mode I/O

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Detailed Description

11. FPGA Awake LED and Suspend Jumper

The suspend mode jumper permits the FPGA to enter an inactive, "suspend" mode. The FPGA Awake LED DS8 will go out when the FPGA enters this mode.

FPGA AWAKE

		2
	LED-		DS8
	LED-	1	DS8
	GRN-S	1			FPGA SUSPEND
	MT	1
			J14 Suspend Jumper

1R88

27.4 OFF = AWAKE (default)

2			1%				ON = SUSPEND	2
			1%				ON = SUSPEND	2
						1/16W
						1/16W

VCC2V5

	R18	H-	2	1
	4.7K
		1X2		J14
	5%

	1/16W

UG518_19_070809

Figure 1-19:FPGA Awake LED and Suspend Jumper

Table 1-15:FPGA Awake/Suspend Mode Jumper Connections

FPGA U1 Pin	Schematic Netname	Suspend Mode I/O

P15	FPGA_AWAKE	Awake LED DS8.2

R16	FPGA_SUSPEND	Suspend J14.2

NET "FPGA_AWAKE"		LOC = "P15";
NET "FPGA_SUSPEND"		LOC = "R16";

Figure 1-20:UCF Location Constraints for FPGA Awake/Suspend Mode Jumper

See the Spartan-6 FPGA Configuration Guide for more information at

http://www.xilinx.com/support/documentation/user_guides/ug380.pdf.

SP601 Hardware User Guide

www.xilinx.com

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UG518 (v1.1) August 19, 2009

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Contents UG518 v1.1 August 19, 2009 optional SP601 Hardware User GuideSP601 Hardware User Guide Date Version Revision Revision HistorySP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Guide Contents About This GuideAdditional Resources Conventions Online Document Preface About This GuideMeaning or Use Example SP601 Evaluation Board OverviewAdditional Information SP601 Evaluation Board FeaturesBlock Diagram Related Xilinx DocumentsRelated Xilinx Documents SP601 Features FeatureDetailed Description Spartan-6 XC6SLX16-2CSG324 Fpga SP601 Features Cont’d NumberDetailed Description 2I/O Voltage Rail of Fpga BanksMB DDR2 Component Memory Schematic Netname Memory U2 5DDR2 Component Memory ConnectionsName 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins 6J12 SPI Flash Programming Header SPI x4 FlashPin # Schematic Netname8UCF Location Constraints for BPI Flash Connections Linear Flash BPIFLASHA6 10UCF Location Constraints for BPI Flash Connections Schematic Netname U3 M88E111 Pin 8PHY Configuration Pins10/100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0SP601 Evaluation Board 9PHY Connections Cont’d Schematic Netname U3 M88E111CP2103GM Connections USB-to-UART Bridge13IIC Bus Topology IIC Bus14UCF Location Constraints for IIC Connections Clock Generation16UCF Location Constraints for Oscillator Socket Connections Vita 57.1 FMC-LPC Connector13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Status LEDs Reference Signal Name Color Label DescriptionFpga Awake LED and Suspend Jumper Suspend Mode I/OControlled LED Fpga Init and Done LEDsUser I/O Reference Signal Name Color Label Fpga PinReference Signal Name Color Label Fpga Pin Designator User DIP switchUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Fpgaprogb Pushbutton Switch Power ManagementAC Adapter and 5V Input Power Jack/Switch Onboard Power Supplies22Estimated Current Draw Rail Estimated Current a Power ManagementJtag Configuration Configuration Options32VITA 57.1 FMC Jtag Bypass Jumper Configuration OptionsSP601 Evaluation Board References Appendix a References Default Jumper and Switch Settings Table B-1Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Vita 57.1 FMC Connections Table C-1VITA 57.1 FMC LPC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn