Xilinx UG518 manual 10UCF Location Constraints for BPI Flash Connections

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Chapter 1: SP601 Evaluation Board

Table 1-7:BPI Memory Connections (Cont’d)

	FPGA U1 Pin	Schematic Netname	BPI Memory U10

			Pin Number	Pin
			Pin Number	Pin

	L17	FLASH_CE_B	14	CE0

	B3	FMC_PWR_GOOD_FLASH_RST_B	16	RP_B

Note: Memory U10 pin 56 address A24 is not connected on the 16 MB device. It is made available for larger density devices.

NET "FLASH_A0"	LOC = "K18";
NET "FLASH_A1"	LOC = "K17";
NET "FLASH_A2"	LOC = "J18";
NET "FLASH_A3"	LOC = "J16";
NET "FLASH_A4"	LOC = "G18";
NET "FLASH_A5"	LOC = "G16";
NET "FLASH_A6"	LOC = "H16";
NET "FLASH_A7"	LOC = "H15";
NET "FLASH_A8"	LOC = "H14";
NET "FLASH_A9"	LOC = "H13";
NET "FLASH_A10"	LOC = "F18";
NET "FLASH_A11"	LOC = "F17";
NET "FLASH_A12"	LOC = "K13";
NET "FLASH_A13"	LOC = "K12";
NET "FLASH_A14"	LOC = "E18";
NET "FLASH_A15"	LOC = "E16";
NET "FLASH_A16"	LOC = "G13";
NET "FLASH_A17"	LOC = "H12";
NET "FLASH_A18"	LOC = "D18";
NET "FLASH_A19"	LOC = "D17";
NET "FLASH_A20"	LOC = "G14";
NET "FLASH_A21"	LOC = "F14";
NET "FLASH_A22"	LOC = "C18";
NET "FLASH_A23"	LOC = "C17";
NET "FLASH_A24"	LOC = "F16";
NET "FPGA_D0_DIN_MISO_MISO1"	LOC = "R13";
NET "FPGA_D1_MISO2"	LOC = "T14";
NET "FPGA_D2_MISO3"	LOC = "V14";
NET "FLASH_D3"	LOC = "U5";
NET "FLASH_D4"	LOC = "V5";
NET "FLASH_D5"	LOC = "R3";
NET "FLASH_D6"	LOC = "T3";
NET "FLASH_D7"	LOC = "R5";
NET "FLASH_WE_B"	LOC = "M16";
NET "FLASH_OE_B"	LOC = "L18";
NET "FLASH_CE_B"	LOC = "L17";
NET "FMC_PWR_GOOD_FLASH_RST_B"	LOC = "B3";

Figure 1-10:UCF Location Constraints for BPI Flash Connections

References

See the Numonyx Flash Memory specifications for more information at

http://www.numonyx.com/Documents/Datasheets/308551_J3D_Discrete_DS.pdf.

In addition, see the Xilinx Spartan-6 Configuration User Guide for more information at http://www.xilinx.com/support/documentation/user_guides/ug380.pdf.

22	www.xilinx.com	SP601 Hardware User Guide
		UG518 (v1.1) August 19, 2009

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Contents SP601 Hardware User Guide UG518 v1.1 August 19, 2009 optionalSP601 Hardware User Guide Revision History Date Version RevisionSP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 About This Guide Guide ContentsAdditional Resources Conventions Preface About This Guide Online DocumentMeaning or Use Example Overview SP601 Evaluation BoardAdditional Information Features SP601 Evaluation BoardRelated Xilinx Documents Block DiagramRelated Xilinx Documents Feature SP601 FeaturesDetailed Description Detailed Description SP601 Features Cont’d NumberSpartan-6 XC6SLX16-2CSG324 Fpga 2I/O Voltage Rail of Fpga BanksMB DDR2 Component Memory 5DDR2 Component Memory Connections Schematic Netname Memory U2Name 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins SPI x4 Flash 6J12 SPI Flash Programming HeaderSchematic Netname Pin #Linear Flash BPI 8UCF Location Constraints for BPI Flash ConnectionsFLASHA6 10UCF Location Constraints for BPI Flash Connections 10/100/1000 Tri-Speed Ethernet PHY 8PHY Configuration PinsSchematic Netname U3 M88E111 Pin Bit2 Bit1 Bit0Schematic Netname U3 M88E111 SP601 Evaluation Board 9PHY Connections Cont’dUSB-to-UART Bridge CP2103GM ConnectionsIIC Bus 13IIC Bus TopologyClock Generation 14UCF Location Constraints for IIC ConnectionsVita 57.1 FMC-LPC Connector 16UCF Location Constraints for Oscillator Socket Connections13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Reference Signal Name Color Label Description Status LEDsSuspend Mode I/O Fpga Awake LED and Suspend JumperFpga Init and Done LEDs Controlled LEDReference Signal Name Color Label Fpga Pin User I/OUser DIP switch Reference Signal Name Color Label Fpga Pin DesignatorUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O AC Adapter and 5V Input Power Jack/Switch Power ManagementFpgaprogb Pushbutton Switch Onboard Power SuppliesPower Management 22Estimated Current Draw Rail Estimated Current aConfiguration Options Jtag ConfigurationConfiguration Options 32VITA 57.1 FMC Jtag Bypass JumperSP601 Evaluation Board References Appendix a References Table B-1Default Jumper and Switch Settings Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Table C-1VITA 57.1 FMC LPC Connections Vita 57.1 FMC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn