Xilinx UG518 manual 4UCF Location Constraints for DDR2 Sdram Data I/O Pins

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Detailed Description

Figure 1-4provides the UCF constraints for the DDR2 SDRAM data pins, including the I/O pin assignment and I/O standard used.

NET "DDR2_DQ15" LOC ="U1"; IOSTANDARD = SSTL18_II ;

NET "DDR2_DQ14" LOC ="U2"; IOSTANDARD = SSTL18_II ;

NET "DDR2_DQ13" LOC ="T1"; IOSTANDARD = SSTL18_II ;

NET "DDR2_DQ12" LOC ="T2"; IOSTANDARD = SSTL18_II ;

NET "DDR2_DQ11" LOC ="N1"; IOSTANDARD = SSTL18_II ;

NET "DDR2_DQ10" LOC ="N2"; IOSTANDARD = SSTL18_II ;

NET "DDR2_DQ9" LOC ="M1"; IOSTANDARD = SSTL18_II ;

NET "DDR2_DQ8" LOC ="M3"; IOSTANDARD = SSTL18_II ;

NET "DDR2_DQ7" LOC ="J1"; IOSTANDARD = SSTL18_II ;

NET "DDR2_DQ6" LOC ="J3"; IOSTANDARD = SSTL18_II ;

NET "DDR2_DQ5" LOC ="H1"; IOSTANDARD = SSTL18_II ;

NET "DDR2_DQ4" LOC ="H2"; IOSTANDARD = SSTL18_II ;

NET "DDR2_DQ3" LOC ="K1"; IOSTANDARD = SSTL18_II ;

NET "DDR2_DQ2" LOC ="K2"; IOSTANDARD = SSTL18_II ;

NET "DDR2_DQ1" LOC ="L1"; IOSTANDARD = SSTL18_II ;

NET "DDR2_DQ0" LOC ="L2"; IOSTANDARD = SSTL18_II ;

Figure 1-4:UCF Location Constraints for DDR2 SDRAM Data I/O Pins

Figure 1-5provides the UCF constraints for the DDR2 SDRAM control pins, including the I/O pin assignment and the I/O standard used.

NET "DDR2_WE_B" LOC ="E3"; IOSTANDARD = SSTL18_II ;

NET "DDR2_UDQS_P" LOC ="P2"; IOSTANDARD = SSTL18_II ;

NET "DDR2_UDQS_N" LOC ="P1"; IOSTANDARD = SSTL18_II ;

NET "DDR2_UDM" LOC ="K4";	IOSTANDARD = SSTL18_II ;
NET "DDR2_RAS_B" LOC ="L5"; IOSTANDARD = SSTL18_II ;
NET "DDR2_ODT" LOC ="K6";	IOSTANDARD = SSTL18_II ;
NET "DDR2_LDQS_P" LOC ="L4"; IOSTANDARD = SSTL18_II ;
NET "DDR2_LDQS_N" LOC ="L3"; IOSTANDARD = SSTL18_II ;
NET "DDR2_LDM" LOC ="K3";	IOSTANDARD = SSTL18_II ;
NET "DDR2_CLK_P" LOC ="G3"; IOSTANDARD = SSTL18_II ;
NET "DDR2_CLK_N" LOC ="G1"; IOSTANDARD = SSTL18_II ;
NET "DDR2_CKE" LOC ="H7";	IOSTANDARD = SSTL18_II ;
NET "DDR2_CAS_B" LOC ="K5"; IOSTANDARD = SSTL18_II ;
NET "DDR2_BA2" LOC ="E1";	IOSTANDARD = SSTL18_II ;
NET "DDR2_BA1" LOC ="F1";	IOSTANDARD = SSTL18_II ;
NET "DDR2_BA0" LOC ="F2";	IOSTANDARD = SSTL18_II ;

Figure 1-5:UCF Location Constraints for DDR2 SDRAM Control Pins

References

See the Elpida DDR2 specifications for more information at

http://www.elpida.com/en/products/details/EDE1116ACBG.html.

Also, see the Spartan-6 FPGA embedded hard memory controller block user guide at

http://www.xilinx.com/support/documentation/user_guides/ug388.pdf.

SP601 Hardware User Guide

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UG518 (v1.1) August 19, 2009

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Contents UG518 v1.1 August 19, 2009 optional SP601 Hardware User GuideSP601 Hardware User Guide Date Version Revision Revision HistorySP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Additional Resources Conventions Guide ContentsAbout This Guide Meaning or Use Example Online DocumentPreface About This Guide Additional Information SP601 Evaluation BoardOverview SP601 Evaluation Board FeaturesRelated Xilinx Documents Block DiagramRelated Xilinx Documents Detailed Description SP601 FeaturesFeature Spartan-6 XC6SLX16-2CSG324 Fpga SP601 Features Cont’d NumberDetailed Description 2I/O Voltage Rail of Fpga Banks MB DDR2 Component Memory Name Schematic Netname Memory U25DDR2 Component Memory Connections 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins 6J12 SPI Flash Programming Header SPI x4 FlashPin # Schematic Netname8UCF Location Constraints for BPI Flash Connections Linear Flash BPIFLASHA6 10UCF Location Constraints for BPI Flash Connections Schematic Netname U3 M88E111 Pin 8PHY Configuration Pins10/100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0SP601 Evaluation Board 9PHY Connections Cont’d Schematic Netname U3 M88E111CP2103GM Connections USB-to-UART Bridge13IIC Bus Topology IIC Bus14UCF Location Constraints for IIC Connections Clock Generation16UCF Location Constraints for Oscillator Socket Connections Vita 57.1 FMC-LPC Connector13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Status LEDs Reference Signal Name Color Label DescriptionFpga Awake LED and Suspend Jumper Suspend Mode I/OControlled LED Fpga Init and Done LEDsUser I/O Reference Signal Name Color Label Fpga PinReference Signal Name Color Label Fpga Pin Designator User DIP switchUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Fpgaprogb Pushbutton Switch Power ManagementAC Adapter and 5V Input Power Jack/Switch Onboard Power Supplies22Estimated Current Draw Rail Estimated Current a Power ManagementJtag Configuration Configuration Options32VITA 57.1 FMC Jtag Bypass Jumper Configuration OptionsSP601 Evaluation Board References Appendix a References Type/Function Default Default Jumper and Switch SettingsTable B-1Default Jumper and Switch Settings Appendix B Default Jumper and Switch Settings LPC Pin Vita 57.1 FMC ConnectionsTable C-1VITA 57.1 FMC LPC Connections FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn