Xilinx Understanding BPI Flash Connections in the SP601 Evaluation Board Manual
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Chapter 1: SP601 Evaluation Board

Figure 1-8provides the UCF constraints for the SPI serial flash PROM.

NET "FPGA_D2_MISO3"

LOC = "V14";

NET "SPI_CS_B"

LOC = "V3";

NET "FPGA_D0_DIN_MISO_MISO1"

LOC = "R13";

NET "FPGA_D1_MISO2"

LOC = "T14";

NET "FPGA_MOSI_CSI_B_MISO0"

LOC = "T13";

NET "FPGA_CCLK"

LOC = "R15";

Figure 1-8:UCF Location Constraints for BPI Flash Connections

References

See the Winbond Serial Flash specifications for more information at http://www.winbond-

usa.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25X64.htm.

See the XPS Serial Peripheral Interface specification for more information at http://www.xilinx.com/support/documentation/ip_documentation/xps_spi.pdf.

4. Linear Flash BPI

An 8-bit (16 MB) Numonyx linear flash memory (TE 28F128J3D-75) (J3D type) is used to provide non-volatile bitstream, code, and data storage. The J3D devices operate at 3.0V; the Spartan-6 FPGA I/Os are 3.3V tolerant and provide electrically compatible logic levels to directly access the linear flash BPI through a 2.5V bank. For details on configuring the FPGA, see “Configuration Options.”

U1

U10

FPGA

BPI FLASH INTERFACE

ADDR, DATA, CTRL

NUMONYX TYPE J3vD

T28F128J3D-75

UG518_09_070809

Figure 1-9:Linear Flash BPI Interface

Table 1-7:BPI Memory Connections

FPGA U1 Pin

Schematic Netname

BPI Memory U10

 

 

Pin Number

Pin

 

 

 

 

 

 

K18

FLASH_A0

32

A0

 

 

 

 

K17

FLASH_A1

28

A1

 

 

 

 

J18

FLASH_A2

27

A2

 

 

 

 

J16

FLASH_A3

26

A3

 

 

 

 

G18

FLASH_A4

25

A4

 

 

 

 

G16

FLASH_A5

24

A5

 

 

 

 

20

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SP601 Hardware User Guide

 

 

UG518 (v1.1) August 19, 2009

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Contents SP601 Hardware User Guide UG518 v1.1 August 19, 2009 optionalSP601 Hardware User Guide Revision History Date Version RevisionSP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Additional Resources Conventions Guide ContentsAbout This Guide Meaning or Use Example Online DocumentPreface About This Guide Additional Information SP601 Evaluation BoardOverview Features SP601 Evaluation BoardRelated Xilinx Documents Block DiagramRelated Xilinx Documents Detailed Description SP601 FeaturesFeature SP601 Features Cont’d Number Spartan-6 XC6SLX16-2CSG324 FpgaDetailed Description 2I/O Voltage Rail of Fpga BanksMB DDR2 Component Memory Name Schematic Netname Memory U25DDR2 Component Memory Connections 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins SPI x4 Flash 6J12 SPI Flash Programming HeaderSchematic Netname Pin #Linear Flash BPI 8UCF Location Constraints for BPI Flash ConnectionsFLASHA6 10UCF Location Constraints for BPI Flash Connections 8PHY Configuration Pins Schematic Netname U3 M88E111 Pin10/100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0Schematic Netname U3 M88E111 SP601 Evaluation Board 9PHY Connections Cont’dUSB-to-UART Bridge CP2103GM ConnectionsIIC Bus 13IIC Bus TopologyClock Generation 14UCF Location Constraints for IIC ConnectionsVita 57.1 FMC-LPC Connector 16UCF Location Constraints for Oscillator Socket Connections13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Reference Signal Name Color Label Description Status LEDsSuspend Mode I/O Fpga Awake LED and Suspend JumperFpga Init and Done LEDs Controlled LEDReference Signal Name Color Label Fpga Pin User I/OUser DIP switch Reference Signal Name Color Label Fpga Pin DesignatorUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Power Management Fpgaprogb Pushbutton SwitchAC Adapter and 5V Input Power Jack/Switch Onboard Power SuppliesPower Management 22Estimated Current Draw Rail Estimated Current aConfiguration Options Jtag ConfigurationConfiguration Options 32VITA 57.1 FMC Jtag Bypass JumperSP601 Evaluation Board References Appendix a References Type/Function Default Default Jumper and Switch SettingsTable B-1Default Jumper and Switch Settings Appendix B Default Jumper and Switch Settings LPC Pin Vita 57.1 FMC ConnectionsTable C-1VITA 57.1 FMC LPC Connections FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn
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