Xilinx UG518 manual SP601 Evaluation Board 9PHY Connections Cont’d, Schematic Netname U3 M88E111

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Chapter 1: SP601 Evaluation Board

Table 1-9:PHY Connections (Cont’d)

	FPGA U1	Schematic Netname	U3 M88E111
	Pin	Schematic Netname	U3 M88E111
	Pin

	P18	PHY_RXD7	120

	A9	PHY_TXC_GTXCLK	14

	B9	PHY_TXCLK	10

	A8	PHY_TXER	13

	B8	PHY_TXCTL_TXEN	16

	F8	PHY_TXD0	18

	G8	PHY_TXD1	19

	A6	PHY_TXD2	20

	B6	PHY_TXD3	24

	E6	PHY_TXD4	25

	F7	PHY_TXD5	26

	A5	PHY_TXD6	28

	C5	PHY_TXD7	29

NET "PHY_COL"	LOC = "L14";
NET "PHY_CRS"	LOC = "M13";
NET "PHY_INT"	LOC = "J13";
NET "PHY_MDC"	LOC = "N14";
NET "PHY_MDIO"	LOC = "P16";
NET "PHY_RESET"	LOC = "L13";
NET "PHY_RXCLK"	LOC = "L16";
NET "PHY_RXCTL_RXDV"	LOC = "N18";
NET "PHY_RXD0"	LOC = "M14";
NET "PHY_RXD1"	LOC = "U18";
NET "PHY_RXD2"	LOC = "U17";
NET "PHY_RXD3"	LOC = "T18";
NET "PHY_RXD4"	LOC = "T17";
NET "PHY_RXD5"	LOC = "N16";
NET "PHY_RXD6"	LOC = "N15";
NET "PHY_RXD7"	LOC = "P18";
NET "PHY_RXER"	LOC = "P17";
NET "PHY_TXCLK"	LOC = "B9";
NET "PHY_TXCTL_TXEN"	LOC = "B8";
NET "PHY_TXC_GTXCLK"	LOC = "A9";
NET "PHY_TXD0"	LOC = "F8";
NET "PHY_TXD1"	LOC = "G8";
NET "PHY_TXD2"	LOC = "A6";
NET "PHY_TXD3"	LOC = "B6";
NET "PHY_TXD4"	LOC = "E6";
NET "PHY_TXD5"	LOC = "F7";
NET "PHY_TXD6"	LOC = "A5";
NET "PHY_TXD7"	LOC = "C5";
NET "PHY_TXER"	LOC = "A8";

Figure 1-11:UCF Location Constraints for PHY Connections

24	www.xilinx.com	SP601 Hardware User Guide
		UG518 (v1.1) August 19, 2009

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Contents SP601 Hardware User Guide UG518 v1.1 August 19, 2009 optionalSP601 Hardware User Guide Revision History Date Version RevisionSP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Guide Contents About This GuideAdditional Resources Conventions Online Document Preface About This GuideMeaning or Use Example SP601 Evaluation Board OverviewAdditional Information Features SP601 Evaluation BoardBlock Diagram Related Xilinx DocumentsRelated Xilinx Documents SP601 Features FeatureDetailed Description SP601 Features Cont’d Number Spartan-6 XC6SLX16-2CSG324 FpgaDetailed Description 2I/O Voltage Rail of Fpga BanksMB DDR2 Component Memory Schematic Netname Memory U2 5DDR2 Component Memory ConnectionsName 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins SPI x4 Flash 6J12 SPI Flash Programming HeaderSchematic Netname Pin #Linear Flash BPI 8UCF Location Constraints for BPI Flash ConnectionsFLASHA6 10UCF Location Constraints for BPI Flash Connections 8PHY Configuration Pins Schematic Netname U3 M88E111 Pin10/100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0Schematic Netname U3 M88E111 SP601 Evaluation Board 9PHY Connections Cont’dUSB-to-UART Bridge CP2103GM ConnectionsIIC Bus 13IIC Bus TopologyClock Generation 14UCF Location Constraints for IIC ConnectionsVita 57.1 FMC-LPC Connector 16UCF Location Constraints for Oscillator Socket Connections13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Reference Signal Name Color Label Description Status LEDsSuspend Mode I/O Fpga Awake LED and Suspend JumperFpga Init and Done LEDs Controlled LEDReference Signal Name Color Label Fpga Pin User I/OUser DIP switch Reference Signal Name Color Label Fpga Pin DesignatorUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Power Management Fpgaprogb Pushbutton SwitchAC Adapter and 5V Input Power Jack/Switch Onboard Power SuppliesPower Management 22Estimated Current Draw Rail Estimated Current aConfiguration Options Jtag ConfigurationConfiguration Options 32VITA 57.1 FMC Jtag Bypass JumperSP601 Evaluation Board References Appendix a References Default Jumper and Switch Settings Table B-1Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Vita 57.1 FMC Connections Table C-1VITA 57.1 FMC LPC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn