Xilinx UG518 manual LPC Pinout

Page 29

Detailed Description

Table 1-13: LPC Pinout

 

K

J

H

G

F

E

D

C

B

A

 

 

 

 

 

 

 

 

 

 

 

1

NC

NC

VREF_A_M2C

GND

NC

NC

PG_C2M

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

2

NC

NC

PRSNT_M2C_L

CLK1_M2C_P

NC

NC

GND

DP0_C2M_P

NC

NC

 

 

 

 

 

 

 

 

 

 

 

3

NC

NC

GND

CLK1_M2C_N

NC

NC

GND

DP0_C2M_N

NC

NC

 

 

 

 

 

 

 

 

 

 

 

4

NC

NC

CLK0_M2C_P

GND

NC

NC

GBTCLK0_M2C_P

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

5

NC

NC

CLK0_M2C_N

GND

NC

NC

GBTCLK0_M2C_N

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

6

NC

NC

GND

LA00_P_CC

NC

NC

GND

DP0_M2C_P

NC

NC

 

 

 

 

 

 

 

 

 

 

 

7

NC

NC

LA02_P

LA00_N_CC

NC

NC

GND

DP0_M2C_N

NC

NC

 

 

 

 

 

 

 

 

 

 

 

8

NC

NC

LA02_N

GND

NC

NC

LA01_P_CC

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

9

NC

NC

GND

LA03_P

NC

NC

LA01_N_CC

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

10

NC

NC

LA04_P

LA03_N

NC

NC

GND

LA06_P

NC

NC

 

 

 

 

 

 

 

 

 

 

 

11

NC

NC

LA04_N

GND

NC

NC

LA05_P

LA06_N

NC

NC

 

 

 

 

 

 

 

 

 

 

 

12

NC

NC

GND

LA08_P

NC

NC

LA05_N

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

13

NC

NC

LA07_P

LA08_N

NC

NC

GND

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

14

NC

NC

LA07_N

GND

NC

NC

LA09_P

LA10_P

NC

NC

 

 

 

 

 

 

 

 

 

 

 

15

NC

NC

GND

LA12_P

NC

NC

LA09_N

LA10_N

NC

NC

 

 

 

 

 

 

 

 

 

 

 

16

NC

NC

LA11_P

LA12_N

NC

NC

GND

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

17

NC

NC

LA11_N

GND

NC

NC

LA13_P

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

18

NC

NC

GND

LA16_P

NC

NC

LA13_N

LA14_P

NC

NC

 

 

 

 

 

 

 

 

 

 

 

19

NC

NC

LA15_P

LA16_N

NC

NC

GND

LA14_N

NC

NC

 

 

 

 

 

 

 

 

 

 

 

20

NC

NC

LA15_N

GND

NC

NC

LA17_P_CC

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

21

NC

NC

GND

LA20_P

NC

NC

LA17_N_CC

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

22

NC

NC

LA19_P

LA20_N

NC

NC

GND

LA18_P_CC

NC

NC

 

 

 

 

 

 

 

 

 

 

 

23

NC

NC

LA19_N

GND

NC

NC

LA23_P

LA18_N_CC

NC

NC

 

 

 

 

 

 

 

 

 

 

 

24

NC

NC

GND

LA22_P

NC

NC

LA23_N

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

25

NC

NC

LA21_P

LA22_N

NC

NC

GND

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

26

NC

NC

LA21_N

GND

NC

NC

LA26_P

LA27_P

NC

NC

 

 

 

 

 

 

 

 

 

 

 

27

NC

NC

GND

LA25_P

NC

NC

LA26_N

LA27_N

NC

NC

 

 

 

 

 

 

 

 

 

 

 

28

NC

NC

LA24_P

LA25_N

NC

NC

GND

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

29

NC

NC

LA24_N

GND

NC

NC

TCK

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

30

NC

NC

GND

LA29_P

NC

NC

TDI

SCL

NC

NC

 

 

 

 

 

 

 

 

 

 

 

31

NC

NC

LA28_P

LA29_N

NC

NC

TDO

SDA

NC

NC

 

 

 

 

 

 

 

 

 

 

 

32

NC

NC

LA28_N

GND

NC

NC

3P3VAUX

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

33

NC

NC

GND

LA31_P

NC

NC

TMS

GND

NC

NC

 

 

 

 

 

 

 

 

 

 

 

SP601 Hardware User Guide

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UG518 (v1.1) August 19, 2009

Image 29
Contents UG518 v1.1 August 19, 2009 optional SP601 Hardware User GuideSP601 Hardware User Guide Date Version Revision Revision HistorySP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Additional Resources Conventions Guide ContentsAbout This Guide Meaning or Use Example Online DocumentPreface About This Guide Additional Information SP601 Evaluation BoardOverview SP601 Evaluation Board FeaturesRelated Xilinx Documents Block DiagramRelated Xilinx Documents Detailed Description SP601 FeaturesFeature Spartan-6 XC6SLX16-2CSG324 Fpga SP601 Features Cont’d NumberDetailed Description 2I/O Voltage Rail of Fpga BanksMB DDR2 Component Memory Name Schematic Netname Memory U25DDR2 Component Memory Connections 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins 6J12 SPI Flash Programming Header SPI x4 FlashPin # Schematic Netname8UCF Location Constraints for BPI Flash Connections Linear Flash BPIFLASHA6 10UCF Location Constraints for BPI Flash Connections Schematic Netname U3 M88E111 Pin 8PHY Configuration Pins10/100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0SP601 Evaluation Board 9PHY Connections Cont’d Schematic Netname U3 M88E111CP2103GM Connections USB-to-UART Bridge13IIC Bus Topology IIC Bus14UCF Location Constraints for IIC Connections Clock Generation16UCF Location Constraints for Oscillator Socket Connections Vita 57.1 FMC-LPC Connector13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Status LEDs Reference Signal Name Color Label DescriptionFpga Awake LED and Suspend Jumper Suspend Mode I/OControlled LED Fpga Init and Done LEDsUser I/O Reference Signal Name Color Label Fpga PinReference Signal Name Color Label Fpga Pin Designator User DIP switchUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Fpgaprogb Pushbutton Switch Power ManagementAC Adapter and 5V Input Power Jack/Switch Onboard Power Supplies22Estimated Current Draw Rail Estimated Current a Power ManagementJtag Configuration Configuration Options32VITA 57.1 FMC Jtag Bypass Jumper Configuration OptionsSP601 Evaluation Board References Appendix a References Type/Function Default Default Jumper and Switch SettingsTable B-1Default Jumper and Switch Settings Appendix B Default Jumper and Switch Settings LPC Pin Vita 57.1 FMC ConnectionsTable C-1VITA 57.1 FMC LPC Connections FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn