Xilinx UG518 manual Vita 57.1 FMC-LPC Connector

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Chapter 1: SP601 Evaluation Board

Oscillator Socket (Single-Ended, 2.5V or 3.3V)

One populated single-ended clock socket (X2) is provided for user applications. The option of 3.3V or 2.5V power may be selected via a 0 ohm resistor selection. The SP601 board is shipped with a 27MHz 2.5V oscillator installed.

NET "USER_CLOCK"

LOC = "V10";

Figure 1-16:UCF Location Constraints for Oscillator Socket Connections

SMA Connectors (Differential)

A high-precision clock signal can be provided to the FPGA using differential clock signals through the onboard 50-ohm SMA connectors J7(P)/J8(N).

NET

"SMACLK_N"

LOC

=

"H18";

NET

"SMACLK_P"

LOC

=

"H17";

Figure 1-17:UCF Location Constraints for SMA Connectors Connections

9. VITA 57.1 FMC-LPC Connector

The VITA 57.1 FMC expansion connector (J1) on the SP601 implements the VITA 57.1.1 LPC format of the VITA 57.1 FMC standard specification. The VITA 57.1 FMC-LPC connector provides 68 single-ended (34 differential) user-defined signals (Table 1-13). The VITA 57.1 FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low Pin Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector form factor is used for both versions. The HPC version has 400 pins present, the LPC version, 160 pins. The Samtec connector system is rated for signaling speeds up to 9 GHz (18 Gb/s) based on a -3dB insertion loss point within a two-level signaling environment. Refer to the Samtec website for data sheets and characterization information for the RoHS- compliant VITA 57.1 FMC-LPC connector (ASP-134603-01) and its mate.

Note that the SP601 board FMC-LPC connector J1 VADJ voltage is FIXED at 2.5V (non- adjustable). This rail cannot be turned off. The SP601 VITA 57.1 FMC interface is compatible with 2.5V Mezzanine Cards capable of supporting 2.5V VADJ.

The SP601 supports all FMC LA Bus connections available on the FMC LPC connector, (LA[00:33]) along with all available FMC M2C clock pairs (CLK0_M2C_P/N and CLK1_M2C_P/N). The SP601 does not support the FMC DP Bus connections since the SP601 does not support any Gigabit Transceivers on the FMC DP Bus. Therefore, DP0_C2M_P/N, DP0_M2C_P/N and GBTCLK0_M2C_P/N are not supported by the SP601 FMC interface.

For more details about FMC, see the VITA57.1 specification available at

http://www.vita.com/fmc.html.

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SP601 Hardware User Guide

 

 

UG518 (v1.1) August 19, 2009

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Contents SP601 Hardware User Guide UG518 v1.1 August 19, 2009 optionalSP601 Hardware User Guide Revision History Date Version RevisionSP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 About This Guide Guide ContentsAdditional Resources Conventions Preface About This Guide Online DocumentMeaning or Use Example Overview SP601 Evaluation BoardAdditional Information Features SP601 Evaluation BoardRelated Xilinx Documents Block DiagramRelated Xilinx Documents Feature SP601 FeaturesDetailed Description SP601 Features Cont’d Number Spartan-6 XC6SLX16-2CSG324 FpgaDetailed Description 2I/O Voltage Rail of Fpga BanksMB DDR2 Component Memory 5DDR2 Component Memory Connections Schematic Netname Memory U2Name 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins SPI x4 Flash 6J12 SPI Flash Programming HeaderSchematic Netname Pin #Linear Flash BPI 8UCF Location Constraints for BPI Flash ConnectionsFLASHA6 10UCF Location Constraints for BPI Flash Connections 8PHY Configuration Pins Schematic Netname U3 M88E111 Pin10/100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0Schematic Netname U3 M88E111 SP601 Evaluation Board 9PHY Connections Cont’d USB-to-UART Bridge CP2103GM ConnectionsIIC Bus 13IIC Bus TopologyClock Generation 14UCF Location Constraints for IIC ConnectionsVita 57.1 FMC-LPC Connector 16UCF Location Constraints for Oscillator Socket Connections13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Reference Signal Name Color Label Description Status LEDsSuspend Mode I/O Fpga Awake LED and Suspend JumperFpga Init and Done LEDs Controlled LEDReference Signal Name Color Label Fpga Pin User I/OUser DIP switch Reference Signal Name Color Label Fpga Pin DesignatorUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Power Management Fpgaprogb Pushbutton SwitchAC Adapter and 5V Input Power Jack/Switch Onboard Power SuppliesPower Management 22Estimated Current Draw Rail Estimated Current aConfiguration Options Jtag ConfigurationConfiguration Options 32VITA 57.1 FMC Jtag Bypass JumperSP601 Evaluation Board References Appendix a References Table B-1Default Jumper and Switch Settings Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Table C-1VITA 57.1 FMC LPC Connections Vita 57.1 FMC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn
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