Xilinx UG518 manual NET Smaclkn

Page 55

NET "PHY_TXCTL_TXEN"	LOC = "B8";
NET "PHY_TXC_GTXCLK"	LOC = "A9";
NET "PHY_TXD0"	LOC = "F8";
NET "PHY_TXD1"	LOC = "G8";
NET "PHY_TXD2"	LOC = "A6";
NET "PHY_TXD3"	LOC = "B6";
NET "PHY_TXD4"	LOC = "E6";
NET "PHY_TXD5"	LOC = "F7";
NET "PHY_TXD6"	LOC = "A5";
NET "PHY_TXD7"	LOC = "C5";
NET "PHY_TXER"	LOC = "A8";
NET "SMACLK_N"	LOC = "H18";
NET "SMACLK_P"	LOC = "H17";
NET "SPI_CS_B"	LOC = "V3";
NET "SYSCLK_N"	LOC = "K16";
NET "SYSCLK_P"	LOC = "K15";
NET "USB_1_CTS"	LOC = "U10";
NET "USB_1_RTS"	LOC = "T5";
NET "USB_1_RX"	LOC = "L12";
NET "USB_1_TX"	LOC = "K14";
NET "USER_CLOCK"	LOC = "V10";

SP601 Hardware User Guide

www.xilinx.com

55

UG518 (v1.1) August 19, 2009

Image 55

Contents UG518 v1.1 August 19, 2009 optional SP601 Hardware User GuideSP601 Hardware User Guide Date Version Revision Revision HistorySP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 About This Guide Guide ContentsAdditional Resources Conventions Preface About This Guide Online DocumentMeaning or Use Example Overview SP601 Evaluation BoardAdditional Information SP601 Evaluation Board FeaturesRelated Xilinx Documents Block DiagramRelated Xilinx Documents Feature SP601 FeaturesDetailed Description 2I/O Voltage Rail of Fpga Banks SP601 Features Cont’d NumberSpartan-6 XC6SLX16-2CSG324 Fpga Detailed DescriptionMB DDR2 Component Memory 5DDR2 Component Memory Connections Schematic Netname Memory U2Name 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins 6J12 SPI Flash Programming Header SPI x4 FlashPin # Schematic Netname8UCF Location Constraints for BPI Flash Connections Linear Flash BPIFLASHA6 10UCF Location Constraints for BPI Flash Connections Bit2 Bit1 Bit0 8PHY Configuration PinsSchematic Netname U3 M88E111 Pin 10/100/1000 Tri-Speed Ethernet PHYSP601 Evaluation Board 9PHY Connections Cont’d Schematic Netname U3 M88E111CP2103GM Connections USB-to-UART Bridge13IIC Bus Topology IIC Bus14UCF Location Constraints for IIC Connections Clock Generation16UCF Location Constraints for Oscillator Socket Connections Vita 57.1 FMC-LPC Connector13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Status LEDs Reference Signal Name Color Label DescriptionFpga Awake LED and Suspend Jumper Suspend Mode I/OControlled LED Fpga Init and Done LEDsUser I/O Reference Signal Name Color Label Fpga PinReference Signal Name Color Label Fpga Pin Designator User DIP switchUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Onboard Power Supplies Power ManagementFpgaprogb Pushbutton Switch AC Adapter and 5V Input Power Jack/Switch22Estimated Current Draw Rail Estimated Current a Power ManagementJtag Configuration Configuration Options32VITA 57.1 FMC Jtag Bypass Jumper Configuration OptionsSP601 Evaluation Board References Appendix a References Table B-1Default Jumper and Switch Settings Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Table C-1VITA 57.1 FMC LPC Connections Vita 57.1 FMC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn