Xilinx UG518 manual USB-to-UART Bridge, CP2103GM Connections

Page 25

Detailed Description

References

See the Marvell Alaska Gigabit Ethernet Transceiver product page for more information at http://www.marvell.com/products/transceivers/alaska_gigabit/index.jsp.

Also, see the Xilinx Tri-Mode Ethernet MAC User Guide at http://www.xilinx.com/support/documentation/ip_documentation/tri_mode_eth_ma c_ug138.pdf.

6. USB-to-UART Bridge

The SP601 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U4) which allows connection to a host computer with a USB cable. The USB cable is supplied in this evaluation kit (Type A end to host computer, Type Mini-B end to SP601 connector J9). Table 1-10details the SP601 J9 pinout.

Xilinx UART IP is expected to be implemented in the FPGA fabric. The FPGA supports the USB-to-UART bridge using four signal pins, transmit (TX), receive (RX), Request to Send (RTS), and Clear to Send (CTS).

Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the CP2103GM USB-to-UART bridge to appear as a COM port to host computer communications application software (for example, HyperTerm or TeraTerm). The VCP device driver must be installed on the host PC prior to establishing communications with the SP601. Refer to the SP601 Getting Started Guide for driver installation instructions.

Table 1-10:USB Type B Pin Assignments and Signal Definitions

USB Connector

Signal Name

Description

Pin

 

 

 

 

 

1

VBUS

+5V from host system (not used)

 

 

 

2

USB_DATA_N

Bidirectional differential serial data (N-side)

 

 

 

3

USB_DATA_P

Bidirectional differential serial data (P-side)

 

 

 

4

GROUND

Signal ground

 

 

 

Table 1-11:

CP2103GM Connections

 

 

 

 

 

 

 

FPGA U1

 

Schematic Netname

U4 CP2103GM

 

Pin

 

 

 

 

 

 

 

 

 

 

 

U10

 

USB_1_CTS

22

 

 

 

 

 

 

T5

 

USB_1_RTS

23

 

 

 

 

 

 

L12

 

USB_1_RX

24

 

 

 

 

 

 

K14

 

USB_1_TX

25

 

 

 

 

 

NET "USB_1_CTS"

LOC = "U10";

NET "USB_1_RTS"

LOC = "T5";

NET "USB_1_RX"

LOC = "L12";

NET "USB_1_TX"

LOC = "K14";

Figure 1-12:UCF Location Constraints for CP2103GM Connections

SP601 Hardware User Guide

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25

UG518 (v1.1) August 19, 2009

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Contents UG518 v1.1 August 19, 2009 optional SP601 Hardware User GuideSP601 Hardware User Guide Date Version Revision Revision HistorySP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 About This Guide Guide ContentsAdditional Resources Conventions Preface About This Guide Online DocumentMeaning or Use Example Overview SP601 Evaluation BoardAdditional Information SP601 Evaluation Board FeaturesRelated Xilinx Documents Block DiagramRelated Xilinx Documents Feature SP601 FeaturesDetailed Description Spartan-6 XC6SLX16-2CSG324 Fpga SP601 Features Cont’d NumberDetailed Description 2I/O Voltage Rail of Fpga BanksMB DDR2 Component Memory 5DDR2 Component Memory Connections Schematic Netname Memory U2Name 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins 6J12 SPI Flash Programming Header SPI x4 FlashPin # Schematic Netname8UCF Location Constraints for BPI Flash Connections Linear Flash BPIFLASHA6 10UCF Location Constraints for BPI Flash Connections Schematic Netname U3 M88E111 Pin 8PHY Configuration Pins10/100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0SP601 Evaluation Board 9PHY Connections Cont’d Schematic Netname U3 M88E111CP2103GM Connections USB-to-UART Bridge13IIC Bus Topology IIC Bus14UCF Location Constraints for IIC Connections Clock Generation16UCF Location Constraints for Oscillator Socket Connections Vita 57.1 FMC-LPC Connector13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Status LEDs Reference Signal Name Color Label DescriptionFpga Awake LED and Suspend Jumper Suspend Mode I/OControlled LED Fpga Init and Done LEDsUser I/O Reference Signal Name Color Label Fpga PinReference Signal Name Color Label Fpga Pin Designator User DIP switchUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Fpgaprogb Pushbutton Switch Power ManagementAC Adapter and 5V Input Power Jack/Switch Onboard Power Supplies22Estimated Current Draw Rail Estimated Current a Power ManagementJtag Configuration Configuration Options32VITA 57.1 FMC Jtag Bypass Jumper Configuration OptionsSP601 Evaluation Board References Appendix a References Table B-1Default Jumper and Switch Settings Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Table C-1VITA 57.1 FMC LPC Connections Vita 57.1 FMC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn
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