Xilinx UG518 manual 3UCF Location Constraints for DDR2 Sdram Address Inputs

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Chapter 1: SP601 Evaluation Board

Table 1-5:DDR2 Component Memory Connections (Cont’d)

FPGA U1	Schematic Netname		Memory U2

		Pin Number		Name
		Pin Number		Name

F2	DDR2_BA0	L2		BA0

F1	DDR2_BA1	L3		BA1

E1	DDR2_BA2	L1		BA2


E3	DDR2_WE_B	K3		WE

L5	DDR2_RAS_B	K7		RAS

K5	DDR2_CAS_B	L7		CAS

K6	DDR2_ODT	K9		ODT

G3	DDR2_CLK_P	J8		CK

G1	DDR2_CLK_N	K8		CK

H7	DDR2_CKE	K2		CKE

L4	DDR2_LDQS_P	F7		LDQS

L3	DDR2_LDQS_N	E8		LDQS

P2	DDR2_UDQS_P	B7		UDQS

P1	DDR2_UDQS_N	A8		UDQS

K3	DDR2_LDM	F3		LDM

K4	DDR2_UDM	B3		UDM

Figure 1-3provides the user constraints file (UCF) for the DDR2 SDRAM address pins, including the I/O pin assignment and the I/O standard used.

NET "DDR2_A12" LOC ="G6"; IOSTANDARD = SSTL18_II ;

NET "DDR2_A11" LOC ="D3"; IOSTANDARD = SSTL18_II ;

NET "DDR2_A10" LOC ="F4"; IOSTANDARD = SSTL18_II ;

NET "DDR2_A9" LOC ="D1"; IOSTANDARD = SSTL18_II ;

NET "DDR2_A8" LOC ="D2"; IOSTANDARD = SSTL18_II ;

NET "DDR2_A7" LOC ="H6"; IOSTANDARD = SSTL18_II ;

NET "DDR2_A6" LOC ="H3"; IOSTANDARD = SSTL18_II ;

NET "DDR2_A5" LOC ="H4"; IOSTANDARD = SSTL18_II ;

NET "DDR2_A4" LOC ="F3"; IOSTANDARD = SSTL18_II ;

NET "DDR2_A3" LOC ="L7"; IOSTANDARD = SSTL18_II ;

NET "DDR2_A2" LOC ="H5"; IOSTANDARD = SSTL18_II ;

NET "DDR2_A1" LOC ="J6"; IOSTANDARD = SSTL18_II ;

NET "DDR2_A0" LOC ="J7"; IOSTANDARD = SSTL18_II ;

Figure 1-3:UCF Location Constraints for DDR2 SDRAM Address Inputs

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		UG518 (v1.1) August 19, 2009

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Contents SP601 Hardware User Guide UG518 v1.1 August 19, 2009 optionalSP601 Hardware User Guide Revision History Date Version RevisionSP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 About This Guide Guide ContentsAdditional Resources Conventions Preface About This Guide Online DocumentMeaning or Use Example Overview SP601 Evaluation BoardAdditional Information Features SP601 Evaluation BoardRelated Xilinx Documents Block DiagramRelated Xilinx Documents Feature SP601 FeaturesDetailed Description SP601 Features Cont’d Number Spartan-6 XC6SLX16-2CSG324 FpgaDetailed Description 2I/O Voltage Rail of Fpga BanksMB DDR2 Component Memory 5DDR2 Component Memory Connections Schematic Netname Memory U2Name 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins SPI x4 Flash 6J12 SPI Flash Programming HeaderSchematic Netname Pin #Linear Flash BPI 8UCF Location Constraints for BPI Flash ConnectionsFLASHA6 10UCF Location Constraints for BPI Flash Connections 8PHY Configuration Pins Schematic Netname U3 M88E111 Pin10/100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0Schematic Netname U3 M88E111 SP601 Evaluation Board 9PHY Connections Cont’dUSB-to-UART Bridge CP2103GM ConnectionsIIC Bus 13IIC Bus TopologyClock Generation 14UCF Location Constraints for IIC ConnectionsVita 57.1 FMC-LPC Connector 16UCF Location Constraints for Oscillator Socket Connections13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Reference Signal Name Color Label Description Status LEDsSuspend Mode I/O Fpga Awake LED and Suspend JumperFpga Init and Done LEDs Controlled LEDReference Signal Name Color Label Fpga Pin User I/OUser DIP switch Reference Signal Name Color Label Fpga Pin DesignatorUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Power Management Fpgaprogb Pushbutton SwitchAC Adapter and 5V Input Power Jack/Switch Onboard Power SuppliesPower Management 22Estimated Current Draw Rail Estimated Current aConfiguration Options Jtag ConfigurationConfiguration Options 32VITA 57.1 FMC Jtag Bypass JumperSP601 Evaluation Board References Appendix a References Table B-1Default Jumper and Switch Settings Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Table C-1VITA 57.1 FMC LPC Connections Vita 57.1 FMC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn