Xilinx UG518 manual User Pushbutton Switches

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Detailed Description

User Pushbutton Switches

The SP601 provides five active high pushbutton switches: SW6, SW4, SW5, SW7 and SW9. The five pushbuttons all have the same topology as the sample shown in Figure 1-25. Four pushbuttons are assigned as GPIO, and the fifth is assigned as a CPU_RESET. Figure 1-25and Table 1-19describe the pushbutton switches.

VCC1V8

Pushbutton

1

CPU_RESET2

P1 P4

P2 P3

4

3

SW9

1 R188

4.7K

5%

2 1/16W

UG518_25_070809

Figure 1-25:User Pushbutton Switch (Typical)

Table 1-19:Pushbutton Switch Connections

FPGA U1 Pin	Schematic Netname	Switch Pin

P4	GPIO_BUTTON_0	SW6.2

F6	GPIO_BUTTON_1	SW4.2

E4	GPIO_BUTTON_2	SW5.2

F5	GPIO_BUTTON_3	SW7.2

N4	CPU_RESET	SW9.2

SP601 Hardware User Guide

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UG518 (v1.1) August 19, 2009

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Contents UG518 v1.1 August 19, 2009 optional SP601 Hardware User GuideSP601 Hardware User Guide Date Version Revision Revision HistorySP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 About This Guide Guide ContentsAdditional Resources Conventions Preface About This Guide Online DocumentMeaning or Use Example Overview SP601 Evaluation BoardAdditional Information SP601 Evaluation Board FeaturesRelated Xilinx Documents Block DiagramRelated Xilinx Documents Feature SP601 FeaturesDetailed Description Spartan-6 XC6SLX16-2CSG324 Fpga SP601 Features Cont’d NumberDetailed Description 2I/O Voltage Rail of Fpga BanksMB DDR2 Component Memory 5DDR2 Component Memory Connections Schematic Netname Memory U2Name 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins 6J12 SPI Flash Programming Header SPI x4 FlashPin # Schematic Netname8UCF Location Constraints for BPI Flash Connections Linear Flash BPIFLASHA6 10UCF Location Constraints for BPI Flash Connections Schematic Netname U3 M88E111 Pin 8PHY Configuration Pins10/100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0SP601 Evaluation Board 9PHY Connections Cont’d Schematic Netname U3 M88E111CP2103GM Connections USB-to-UART Bridge13IIC Bus Topology IIC Bus14UCF Location Constraints for IIC Connections Clock Generation16UCF Location Constraints for Oscillator Socket Connections Vita 57.1 FMC-LPC Connector13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Status LEDs Reference Signal Name Color Label DescriptionFpga Awake LED and Suspend Jumper Suspend Mode I/O Controlled LED Fpga Init and Done LEDsUser I/O Reference Signal Name Color Label Fpga PinReference Signal Name Color Label Fpga Pin Designator User DIP switchUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Fpgaprogb Pushbutton Switch Power ManagementAC Adapter and 5V Input Power Jack/Switch Onboard Power Supplies22Estimated Current Draw Rail Estimated Current a Power ManagementJtag Configuration Configuration Options32VITA 57.1 FMC Jtag Bypass Jumper Configuration OptionsSP601 Evaluation Board References Appendix a References Table B-1Default Jumper and Switch Settings Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Table C-1VITA 57.1 FMC LPC Connections Vita 57.1 FMC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn