Chapter 3 | Hardware |
J1 | Signal | PCI | Description |
Pin # |
| Pin # |
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| GNT* | 17 (A17) | Grant – This is a |
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| access to the bus has been granted. Every master has its own GNT, |
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| which must be ignored while RST is asserted. |
| Ground | 18 (A18) | Ground |
57 | PME* | 19 (A19) | Power Management Event – This signal is an optional signal that can |
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| be used by a device to request a change in the device or system |
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| power state. |
91 | AD30 | 20 (A20) | Address/Data bus 30 – These signals (AD31 – AD0) are multiplexed |
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| on the same PCI connector pins. During the address phase of a PCI |
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| cycle, |
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| information. During the data phase, AD31 – AD0 contain data. |
| +3.3V | 21 (A21) | +3.3 Volt Power |
87 | AD28 | 22 (A22) | Address/Data bus 28 – Refer to |
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86 | AD26 | 23 (A23) | Address/Data bus 26 – Refer to |
| Ground | 24 (A24) | Ground |
81 | AD24 | 25 (A25) | Address/Data bus 24 – Refer to |
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60 | DEVSEL | 26 (A26) | Initialization Device Select – This signal is used as a chip select |
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| during configuration read and write transactions. |
| +3.3V | 27 (A27) | +3.3 Volt Power |
77 | AD22 | 28 (A28) | Address/Data bus 22 – Refer to |
75 | AD20 | 29 (A29) | Address/Data bus 20 – Refer to |
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| Ground | 30 (A30) | Ground |
74 | AD18 | 31 (A31) | Address/Data bus 18 – Refer to |
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69 | AD16 | 32 (A32) | Address/Data bus 16 – Refer to |
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| +3.3V | 33 (A33) | +3.3 Volt Power |
65 | FRAME* | 34 (A34) | PCI bus Frame access – This signal is driven by the current master to |
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| indicate the start of a transaction and will remain active until the |
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| final data cycle. |
| Ground | 35 (A35) | Ground |
61 | TRDY* | 36 (A36) | Target Ready – This signal indicates the selected device’s ability to |
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| complete the current cycle of transaction. Both IRDY* and TRDY* |
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| must be asserted to terminate a data cycle. |
| Ground | 37 (A37) | Ground |
64 | STOP* | 38 (A38) | Stop – This signal is driven by the current PCI target to request the |
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| master to stop the current transaction. |
| +3.3V | 39 (A39) | +3.3 Volt Power |
| Reserved* | 40 (A40) | Reserved |
| Reserved* | 41 (A41) | Reserved |
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| Ground | 42 (A42) | Ground |
53 | PAR | 43 (A43) | PCI bus Parity bit – This signal is the even parity bit on AD[31:0] |
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| and CBE[3:0]*. |
47 | AD15 | 44 (A44) | Address/Data bus 15 – Refer to |
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| +3.3V | 45 (A45) | +3.3 Volt Power |
20 | Reference Manual | XTX 820 |