Texas Instruments TMS320C6712D manuals
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Texas Instruments TMS320C6712D Warranty
102 pages 1.37 Mb
D D D D D 3.3-V I/Os, 1.20 3 D D8 D60 Dreset 61 absolute maximum ratings over operating case temperature range (unless otherwise noted)recommended operating conditions 62 63 PARAMETER MEASUREMENT INFORMATION signal transition levels 64 PARAMETER MEASUREMENT INFORMATION (CONTINUED) AC transient rise/fall time specifications 65 timing parameters and board routing analysis 66 PARAMETER MEASUREMENT INFORMATION (CONTINUED)Table 34. Board-Level Timings Figure 20. Board-Level Input/Output Timings 67 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN (see Figure 21)Figure 21. CLKIN Timings Figure 22. CLKOUT2 Timings switching characteristics over recommended operating conditions for CLKOUT2 (see Figure 22) Figure 23. CLKOUT3 Timings Figure 24. ECLKIN Timings 68 timing requirements for ECLKIN (see Figure 24) 69 Figure 25. ECLKOUT Timings71 ASYNCHRONOUS MEMORY TIMING (CONTINUED)Figure 26. Asynchronous Memory Read Timing 72 ASYNCHRONOUS MEMORY TIMING (CONTINUED)Figure 27. Asynchronous Memory Write Timing 74 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)Figure 28. SBSRAM Read Timing Figure 29. SBSRAM Write Timing 75 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 30)76 Figure 30. SDRAM Read Command (CAS Latency 3)77 Figure 31. SDRAM Write Command78 Figure 32. SDRAM ACTV CommandFigure 33. SDRAM DCAB Command 79 Figure 34. SDRAM DEAC CommandFigure 35. SDRAM REFR Command 80 Figure 36. SDRAM MRS Command81 HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles (see Figure 37)Figure 37. HOLD/HOLDA Timing 82 Figure 38. BUSREQ Timing83 RESET TIMING timing requirements for reset (see Figure 39) switching characteristics over recommended operating conditions during reset (see Figure 39) 84 RESET TIMING (CONTINUED)85 EXTERNAL INTERRUPT TIMING timing requirements for external interrupts (see Figure 40)Figure 40. External/NMI Interrupt Timing 86 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP (see Figure 41)88 Figure 41. McBSP Timings89 timing requirements for FSR when GSYNC = 1 (see Figure 42)Figure 42. FSR Timing When GSYNC = 1 timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 43) 90 slave: CLKSTP = 10b, CLKXP = 0 (see Figure 43) Figure 43. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 44) 91 slave: CLKSTP = 11b, CLKXP = 0 (see Figure 44) Figure 44. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 92 timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 45)slave: CLKSTP = 10b, CLKXP = 1 (see Figure 45) Figure 45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 93 timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 46)slave: CLKSTP = 11b, CLKXP = 1 (see Figure 46) 95 TIMER TIMING timing requirements for timer inputs (see Figure 47)switching characteristics over recommended operating conditions for timer outputs (see Figure 47) 96 switching characteristics over recommended operating conditions for GPIO outputs (see Figure 48)Figure 48. GPIO Port Timing 97 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 49)switching characteristics over recommended operating conditions for JTAG test port (see Figure 49)Figure 49. JTAG Test-Port Timing 98 MECHANICAL DATA package thermal resistance characteristicsthermal resistance characteristics (S-PBGA package) for GDP thermal resistance characteristics (S-PBGA package) for ZDP packaging information PACKAGING INFORMATION 99 PACKAGE OPTION ADDENDUM100 MECHANICAL DATAGDP (SPBGAN272) PLASTIC BALL GRID ARRAY 101 MECHANICAL DATAZDP (SPBGAN272) PLASTIC BALL GRID ARRAY
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