Texas Instruments TMS320C6712D warranty CPU CSR Register Bit Field Description, Cpu Id, Pcc

Models: TMS320C6712D

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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

 

 

 

 

 

 

CPU CSR register description (continued)

 

 

 

Table 17. CPU CSR Register Bit Field Description

 

 

 

 

 

 

 

 

 

BIT #

NAME

 

 

 

 

DESCRIPTION

 

 

 

 

 

31:24

CPU ID

CPU ID + REV ID. Read only.

 

Identifies which CPU is used and defines the silicon revision of the CPU.

 

 

 

 

23:16

REVISION ID

CPU ID + REVISION ID (31:16) are combined for a value of: 0x0203

 

 

 

 

 

 

 

 

 

 

Control power-down modes. The values are always read as zero.

 

 

 

000000

=

no power-down (default)

 

15:10

PWRD

001001

=

PD1, wake-up by an enabled interrupt

 

010001

=

PD1, wake-up by an enabled or not enabled interrupt

 

 

 

 

 

 

011010

=

PD2, wake-up by a device reset

 

 

 

011100

=

PD3, wake-up by a device reset

 

 

 

Others

 

=

Reserved

 

 

 

 

 

 

 

 

 

Saturate bit.

 

 

 

 

 

Set when any unit performs a saturate. This bit can be cleared only by the MVC instruction and can

 

9

SAT

be set only by a functional unit. The set by the a functional unit has priority over a clear (by the MVC

 

 

 

instruction) if they occur on the same cycle. The saturate bit is set one full cycle (one delay slot) after

 

 

 

a saturate occurs. This bit will not be modified by a conditional instruction whose condition is false.

 

 

 

 

 

 

 

Endian bit. This bit is read-only.

 

8

EN

Depicts the device endian mode.

 

0

=

Big Endian mode.

 

 

 

 

 

 

1

=

Little Endian mode [default].

 

 

 

 

 

 

 

Program Cache control mode.

 

7:5

PCC

L1D, Level 1 Program Cache

 

000/010

=

Cache Enabled / Cache accessed and updated on reads.

 

 

 

 

 

 

All other PCC values reserved.

 

 

 

 

 

 

 

Data Cache control mode.

 

4:2

DCC

L1D, Level 1 Data Cache

 

000/010

=

Cache Enabled / 2-Way Cache

 

 

 

 

 

 

All other DCC values reserved

 

 

 

 

 

 

 

Previous GIE (global interrupt enable); saves the Global Interrupt Enable (GIE) when an interrupt is

 

 

 

taken. Allows for proper nesting of interrupts.

 

1

PGIE

 

 

 

 

 

 

 

 

0

=

Previous GIE value is 0. (default)

 

 

 

1

=

Previous GIE value is 1.

 

 

 

 

 

 

 

Global interrupt enable bit.

 

 

 

Enables (1) or disables (0) all interrupts except the reset interrupt and NMI (nonmaskable interrupt).

 

0

GIE

 

 

 

 

 

 

 

 

0

=

Disables all interrupts (except the reset interrupt and NMI) [default]

 

 

 

1

=

Enables all interrupts (except the reset interrupt and NMI)

 

 

 

 

 

 

 

 

 

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Texas Instruments TMS320C6712D warranty CPU CSR Register Bit Field Description, Cpu Id, Pcc

TMS320C6712D specifications

The Texas Instruments TMS320C6712D is a high-performance, fixed-point digital signal processor (DSP) that belongs to the TMS320C6000 family, well known for its advanced processing capabilities tailored for demanding signal processing applications. Launched in the early 2000s, the C6712D combines high computational power with a rich set of features, making it suitable for a variety of applications such as telecommunications, audio processing, and industrial control systems.

One of the standout characteristics of the TMS320C6712D is its architecture, which is based on a highly efficient VLIW (Very Long Instruction Word) design. This architecture allows the processor to execute multiple instructions in a single clock cycle, significantly increasing performance. The device operates at clock speeds of up to 150 MHz, providing substantial computational throughput that can handle complex algorithms and real-time processing tasks.

Another key feature of the TMS320C6712D is its 32-bit fixed-point processing capabilities, which allows it to perform difficult mathematical computations efficiently. With an instruction set optimized for DSP applications, the processor includes specialized instructions for multiplying and accumulating operations, as well as support for advanced filtering and generation of audio signals.

The C6712D offers an extensive memory architecture, supporting up to 128 MB of external memory via a 32-bit data bus. It features on-chip SRAM, which provides fast access to data and program storage, enhancing the system's overall performance. Additionally, the device includes a powerful set of peripherals, such as dual asynchronous serial ports (UART), I2C interfaces, and DSP-specific interfaces that facilitate connectivity with other components and systems.

Power consumption is another vital aspect of the TMS320C6712D. It incorporates technologies allowing for low-power operation, which is essential for portable and battery-operated devices. The capability to operate in various power modes helps optimize performance while minimizing energy usage.

In conclusion, the Texas Instruments TMS320C6712D is a versatile and powerful DSP that excels in high-performance applications. Its VLIW architecture, fixed-point processing capabilities, extensive memory options, and low power consumption make it an ideal choice for engineers looking to implement complex signal processing tasks efficiently. Whether used in telecommunications, audio processing, or industrial applications, the C6712D remains a reliable and capable solution in the digital signal processing landscape.