Texas Instruments TMS320C6712D warranty Emif device speed, Example Boards and Maximum Emif Speed

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

EMIF device speed

The maximum EMIF speed on the device is 100 MHz. TI recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings to determine if the maximum EMIF speed is achievable for a given board layout. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839).

For ease of design evaluation, Table 33 contains IBIS simulation results showing the maximum EMIF-SDRAM interface speeds for the given example boards (TYPE) and SDRAM speed grades. Timing analysis should be performed to verify that all AC timings are met for the specified board layout. Other configurations are also possible, but again, timing analysis must be done to verify proper AC timings.

To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see the Terminal Functions table for the EMIF output signals).

Table 33. Example Boards and Maximum EMIF Speed

	BOARD CONFIGURATION			MAXIMUM ACHIEVABLE
TYPE	EMIF INTERFACE	BOARD TRACE	SDRAM SPEED GRADE	EMIF-SDRAM
	COMPONENTS			INTERFACE SPEED
			143 MHz 32-bit SDRAM (−7)	100 MHz
1-Load	One bank of one	1 to 3-inch traces with proper	166 MHz 32-bit SDRAM (−6)	For short traces, SDRAM data
				output hold time on these
		termination resistors;
Short Traces	32-Bit SDRAM		183 MHz 32-bit SDRAM (−55)	SDRAM speed grades cannot
		Trace impedance ~ 50 Ω
				meet EMIF input hold time
			200 MHz 32-bit SDRAM (−5)
				requirement (see NOTE 1).
			125 MHz 16-bit SDRAM (−8E)	100 MHz
		1.2 to 3 inches from EMIF to
2-Loads	One bank of two		133 MHz 16-bit SDRAM (−75)	100 MHz
		each load, with proper
			143 MHz 16-bit SDRAM (−7E)	100 MHz
Short Traces	16-Bit SDRAMs	termination resistors;
			167 MHz 16-bit SDRAM (−6A)	100 MHz
		Trace impedance ~ 78 Ω
			167 MHz 16-bit SDRAM (−6)	100 MHz
				For short traces, EMIF cannot
			125 MHz 16-bit SDRAM (−8E)	meet SDRAM input hold
				requirement (see NOTE 1).
		1.2 to 3 inches from EMIF to
3-Loads	One bank of two		133 MHz 16-bit SDRAM (−75)	100 MHz
		each load, with proper
	32-Bit SDRAMs		143 MHz 16-bit SDRAM (−7E)	100 MHz
Short Traces		termination resistors;
	One bank of buffer
			167 MHz 16-bit SDRAM (−6A)	100 MHz
		Trace impedance ~ 78 Ω
				For short traces, EMIF cannot
			167 MHz 16-bit SDRAM (−6)	meet SDRAM input hold
				requirement (see NOTE 1).
			143 MHz 32-bit SDRAM (−7)	83 MHz
	One bank of one
			166 MHz 32-bit SDRAM (−6)	83 MHz
	32-Bit SDRAM
3-Loads		4 to 7 inches from EMIF;
			183 MHz 32-bit SDRAM (−55)	83 MHz
	One bank of one
Long Traces		Trace impedance ~ 63 Ω
	32-Bit SBSRAM			SDRAM data output hold time
	One bank of buffer		200 MHz 32-bit SDRAM (−5)	cannot meet EMIF input hold
				requirement (see NOTE 1).

NOTE 1: Results are based on IBIS simulations for the given example boards (TYPE). Timing analysis should be performed to determine if timing requirements can be met for the particular system.

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