Texas Instruments TMS320C6712D warranty Synchronous Dram Timing, 150

		SPRS293A − OCTOBER	2005 − REVISED NOVEMBER 2005
		SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles† (see Figure 30)
NO.				-150		UNIT
				MIN	MAX
6	tsu(EDV-EKOH)	Setup time, read EDx valid before ECLKOUT high		1.5		ns
7	th(EKOH-EDV)	Hold time, read EDx valid after ECLKOUT high		2.5		ns

†The SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.

switching characteristics over recommended operating conditions for synchronous DRAM cycles†‡ (see Figure 30−Figure 36)

NO.		PARAMETER						−150		UNIT
								MIN	MAX
1	td(EKOH-CEV)	Delay time, ECLKOUT high to			valid			1.5	7	ns
			CEx
2	td(EKOH-BEV)	Delay time, ECLKOUT high to			valid				7	ns
			BEx
3	td(EKOH-BEIV)	Delay time, ECLKOUT high to			invalid			1.5		ns
			BEx
4	td(EKOH-EAV)	Delay time, ECLKOUT high to EAx valid							7	ns
5	td(EKOH-EAIV)	Delay time, ECLKOUT high to EAx invalid						1.5		ns
8	td(EKOH-CASV)	Delay time, ECLKOUT high to						1.5	7	ns
						ARE/SDCAS/SSADS valid
9	td(EKOH-EDV)	Delay time, ECLKOUT high to		valid					7	ns
			EDx
10	td(EKOH-EDIV)	Delay time, ECLKOUT high to		invalid				1.5		ns
			EDx
11	td(EKOH-WEV)	Delay time, ECLKOUT high to						1.5	7	ns
			AWE/SDWE/SSWE valid
12	td(EKOH-RAS)	Delay time, ECLKOUT high to,						1.5	7	ns
							AOE/SDRAS/SSOE valid

†The SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.

‡ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.

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