SPRS293 − OCTOBER 2005

GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING

timing requirements for GPIO inputs†‡

(see Figure 48)

 

 

NO.

 

 

 

−150

 

UNIT

 

 

 

 

 

 

 

 

MIN

MAX

 

 

 

 

 

 

 

 

 

 

 

 

1

tw(GPIH)

Pulse duration, GPIx high

 

4P

 

ns

2

tw(GPIL)

Pulse duration, GPIx low

 

4P

 

ns

P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.

The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to at least 24P to allow the DSP enough time to access the GPIO register through the CFGBUS.

switching characteristics over recommended operating conditions for GPIO outputs†§ (see Figure 48)

NO.

 

PARAMETER

−150

 

UNIT

 

 

 

 

MIN

MAX

 

 

 

 

 

 

 

 

 

 

3

tw(GPOH)

Pulse duration, GPOx high

12P − 3

 

ns

4

tw(GPOL)

Pulse duration, GPOx low

12P − 3

 

ns

P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.

§The number of CFGBUS cycles between two back-to-back CFGBUS writes to the GPIO register is 12 SYSCLK1 cycles; therefore, the minimum GPOx pulse width is 12P.

GPIx

GPOx

2 1

4

3

Figure 48. GPIO Port Timing

96

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Texas Instruments TMS320C6712D GENERAL-PURPOSE INPUT/OUTPUT Gpio Port Timing, Timing requirements for Gpio inputs†‡

TMS320C6712D specifications

The Texas Instruments TMS320C6712D is a high-performance, fixed-point digital signal processor (DSP) that belongs to the TMS320C6000 family, well known for its advanced processing capabilities tailored for demanding signal processing applications. Launched in the early 2000s, the C6712D combines high computational power with a rich set of features, making it suitable for a variety of applications such as telecommunications, audio processing, and industrial control systems.

One of the standout characteristics of the TMS320C6712D is its architecture, which is based on a highly efficient VLIW (Very Long Instruction Word) design. This architecture allows the processor to execute multiple instructions in a single clock cycle, significantly increasing performance. The device operates at clock speeds of up to 150 MHz, providing substantial computational throughput that can handle complex algorithms and real-time processing tasks.

Another key feature of the TMS320C6712D is its 32-bit fixed-point processing capabilities, which allows it to perform difficult mathematical computations efficiently. With an instruction set optimized for DSP applications, the processor includes specialized instructions for multiplying and accumulating operations, as well as support for advanced filtering and generation of audio signals.

The C6712D offers an extensive memory architecture, supporting up to 128 MB of external memory via a 32-bit data bus. It features on-chip SRAM, which provides fast access to data and program storage, enhancing the system's overall performance. Additionally, the device includes a powerful set of peripherals, such as dual asynchronous serial ports (UART), I2C interfaces, and DSP-specific interfaces that facilitate connectivity with other components and systems.

Power consumption is another vital aspect of the TMS320C6712D. It incorporates technologies allowing for low-power operation, which is essential for portable and battery-operated devices. The capability to operate in various power modes helps optimize performance while minimizing energy usage.

In conclusion, the Texas Instruments TMS320C6712D is a versatile and powerful DSP that excels in high-performance applications. Its VLIW architecture, fixed-point processing capabilities, extensive memory options, and low power consumption make it an ideal choice for engineers looking to implement complex signal processing tasks efficiently. Whether used in telecommunications, audio processing, or industrial applications, the C6712D remains a reliable and capable solution in the digital signal processing landscape.