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Texas Instruments TMS320C6712D warranty MRS Eclkout, CE30 BE10 EA212 MRS value ED150

Models: TMS320C6712D

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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

SYNCHRONOUS DRAM TIMING (CONTINUED)

	MRS
ECLKOUT
	1	1
CE[3:0]
BE[1:0]
	4	5
EA[21:2]	MRS value
ED[15:0]
	12	12
AOE/SDRAS/SSOE†
	8	8
ARE/SDCAS/SSADS†
	11	11
AWE/SDWE/SSWE†

†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.

Figure 36. SDRAM MRS Command

80	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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Texas Instruments TMS320C6712D warranty MRS Eclkout, CE30 BE10 EA212 MRS value ED150

Contents

SPRS293A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONSMultichannel Buffered Serial Port Timing Bottom View GDP and ZDP BGA package bottom viewGDP and ZDP 272-PIN Ball Grid Array BGA Package Description Device characteristics Characteristics of the C6712D ProcessorHardware Features Internal Clock C6712DDevice compatibility Functional block and CPU DSP core diagram Digital Signal ProcessorCPU DSP core description ST1 DA1DA2 ST2Memory Block Description Block Size Bytes HEX Address Range Memory map summaryMemory Map Summary Peripheral register descriptions Emif RegistersL2 Cache Registers HEX Address Range Acronym Register NameInterrupt Selector Registers Device RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name CommentsEdma Registers Quick DMA Qdma and Pseudo Registers†PLL Controller Registers Gpio RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 and McBSP1 RegistersSignal groups description Clkin CLKOUT3 CLKOUT2† CLKMODE0 Pllhv TMS TDO TDI TCK TrstJtag BIG/LITTLE EndianTOUT1 TINP1 CLKR1CLKS1† GpioDevice Configurations Device configurations at device resetConfiguration GDP/ZDP Functional Description PIN BOOTMODE10Emifbe LendianBIT # Name Description Devcfg register descriptionEksrc Terminal Functions IPD Description Name GDP IPU‡ ZDP PIN SignalTerminal Functions Bootmode BOOTMODE1 C19 BOOTMODE0 C20 IPDEMU1B9 EMU0D9 IPU LITTLE/BIG Endian FormatIPD Description Name GDP IPU‡ ZDP Resets and Interrupts Only one asserted during any external data accessEdge-driven Decoded from the two lowest bits of the internal addressEmif − Address # Emif − Data #TIMER1 TIMER0IPD Description Name GDP IPU‡ ZDP Emif − Data # Multichannel Buffered Serial Port 1 McBSP1Reserved for Test Multichannel Buffered Serial Port 0 McBSP0GENERAL-PURPOSE INPUT/OUTPUT Gpio Module IPD Description Name GDP IPU ZDP RSV IPURSV IPD Additional Reserved for TestSPRS293A − October 2005 − Revised November Name GDP ZDP Supply Voltage Pins See the power-supply decoupling portion of this data sheetDvdd CvddDescription Name GDP ZDP Supply Voltage Pins Ground PinsVSS GNDSignal Name PIN GDP ZDP TYPE† VSS GNDDescription GDP Name ZDP Ground Pins VSSHardware Development Tools Development supportSoftware Development Tools Fully qualified production device Device supportDevice and development-support tool nomenclature Temperature Range Default 0C to 90C PrefixDevice Family TechnologyDocumentation support CPU CSR register description Revision IDPwrd PCC DCC Pgie GIEPCC CPU CSR Register Bit Field DescriptionCPU ID L2MODE Cache configuration Ccfg register descriptionCcfg Register Bit Field Description DSP Interrupt Default Selector Module Control Interrupt sources and interrupt selectorDSP Interrupts Interrupt Selector EventEdma Selector Edma module and Edma selectorEdma Channels ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0CPLL and PLL controller PLL Lock and Reset Times Clkout Signals, Default Settings, and ControlEnabled or Disabled MIN TYP MAX UnitGDP 150and ZDP Clock SignalPLL Clock Frequency Ranges†‡ Pllcsr Register 0x01B7 C100 PLL Control/Status Register PllcsrPllm Register 0x01B7 C110 PLL Multiplier Control Register PllmDxEN OD1EN OSCDIV1 Register 0x01B7 C124Oscillator Divider 1 Register OSCDIV1 DIR General-purpose input/output GpioGP7 GP6 GP5 GP4 GP2 Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1Power-supply sequencing Characteristics of the Power-Down ModesPower-supply design considerations System-level design considerationsPower-supply decoupling Supply Schottky Diode Core SupplyGND Dvdd C6000Ieee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif SpeedEmif big endian mode correctness BootmodeReset Emif Data Lines Pins Where Data PresentIOH Recommended operating conditionsMIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX Unit IOZSignal transition levels Parameter Measurement Information42 Ω Vref = 1.5AC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max GroundTiming parameters and board routing analysis Output from DSP Control Signals † Output from DSPBoard-Level Timings Example see Figure See Figure Input and Output ClocksTiming requirements for CLKIN†‡§ Timing requirements for ECLKIN§ see Figure Clkin CLKOUT3MIN Eclkin EclkoutAsynchronous Memory Timing Timing requirements for asynchronous memory cycles†‡See −Figure AreSetup = Strobe = Not Ready Hold = CE30 BE10 EA212ED150 Read Data AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† ArdyAOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy CEx BE30 EA212ED310 SYNCHRONOUS-BURST Memory Timing Unit MIN MAXCE30 BE10 BE1 BE2 BE3 BE4EA212 ED150 ARE/SDCAS/SSADS † AOE/SDRAS/SSOE † AWE/SDWE/SSWE†150 Synchronous Dram TimingTiming requirements for synchronous Dram cycles† see Figure AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Read EclkoutEA2113 Bank EA112 Column EA12 ED150 Write Eclkout EA2113EA12 ED150 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †Actv Eclkout CE30 BE10 EA2113 Bank Activate EA112 Row Address EA12 ED150AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab EclkoutDeac Eclkout CE30 BE10 EA2113EA112 EA12 ED150 Refr EclkoutMRS Eclkout CE30 BE10 EA212 MRS value ED150HOLD/HOLDA Timing Timing requirements for the HOLD/HOLDA cycles† see FigureHold Hold HoldaBusreq Timing Eclkout BusreqCLKMODE0 = Reset TimingTiming requirements for reset†‡ see Figure Phase Emif Z Group † Emif Low Group † Boot and DeviceEXTINT, NMI External Interrupt TimingTiming requirements for external interrupts† see Figure Multichannel Buffered Serial Port Timing Timing requirements for McBSP†‡ see FigureParameter Clks Clkr FSR intBitn-1 ClkxTiming requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave Unit MIN MAXBit Bitn-1 Parameter MASTER§ Slave Unit MIN MAXClkx FSX McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Multichannel Buffered Serial Port Timing McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = TINPx TOUTx Timer TimingTiming requirements for timer inputs† GPIx GPOx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingTiming requirements for Gpio inputs†‡ Unit MIN MAX TCK TDO TDI/TMS/TRST Jtag TEST-PORT TimingTiming requirements for Jtag test port see Figure Package thermal resistance characteristics Thermal resistance characteristics S-PBGA package for GDPThermal resistance characteristics S-PBGA package for ZDP Mechanical DataOrderable Device Status Package Pins Package Eco Plan Packaging InformationMSL Peak Temp QtyGDP S-PBGA-N272 Seating Plane 4204396/A 04/02ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02Important Notice

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

SYNCHRONOUS DRAM TIMING (CONTINUED)

MRS

ECLKOUT

CE[3:0]

BE[1:0]

EA[21:2]

MRS value

ED[15:0]

AOE/SDRAS/SSOE†

Figure 36. SDRAM MRS Command