MRS Eclkout | Texas Instruments TMS320C6712D manual

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

SYNCHRONOUS DRAM TIMING (CONTINUED)

	MRS
ECLKOUT
	1	1
CE[3:0]
BE[1:0]
	4	5
EA[21:2]	MRS value
ED[15:0]
	12	12
AOE/SDRAS/SSOE†
	8	8
ARE/SDCAS/SSADS†
	11	11
AWE/SDWE/SSWE†

†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.

Figure 36. SDRAM MRS Command

80	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Page 80

Image 80

Texas Instruments TMS320C6712D warranty MRS Eclkout, CE30 BE10 EA212 MRS value ED150

TMS320C6712D specifications

The Texas Instruments TMS320C6712D is a high-performance, fixed-point digital signal processor (DSP) that belongs to the TMS320C6000 family, well known for its advanced processing capabilities tailored for demanding signal processing applications. Launched in the early 2000s, the C6712D combines high computational power with a rich set of features, making it suitable for a variety of applications such as telecommunications, audio processing, and industrial control systems.

One of the standout characteristics of the TMS320C6712D is its architecture, which is based on a highly efficient VLIW (Very Long Instruction Word) design. This architecture allows the processor to execute multiple instructions in a single clock cycle, significantly increasing performance. The device operates at clock speeds of up to 150 MHz, providing substantial computational throughput that can handle complex algorithms and real-time processing tasks.

Another key feature of the TMS320C6712D is its 32-bit fixed-point processing capabilities, which allows it to perform difficult mathematical computations efficiently. With an instruction set optimized for DSP applications, the processor includes specialized instructions for multiplying and accumulating operations, as well as support for advanced filtering and generation of audio signals.

The C6712D offers an extensive memory architecture, supporting up to 128 MB of external memory via a 32-bit data bus. It features on-chip SRAM, which provides fast access to data and program storage, enhancing the system's overall performance. Additionally, the device includes a powerful set of peripherals, such as dual asynchronous serial ports (UART), I2C interfaces, and DSP-specific interfaces that facilitate connectivity with other components and systems.

Power consumption is another vital aspect of the TMS320C6712D. It incorporates technologies allowing for low-power operation, which is essential for portable and battery-operated devices. The capability to operate in various power modes helps optimize performance while minimizing energy usage.

In conclusion, the Texas Instruments TMS320C6712D is a versatile and powerful DSP that excels in high-performance applications. Its VLIW architecture, fixed-point processing capabilities, extensive memory options, and low power consumption make it an ideal choice for engineers looking to implement complex signal processing tasks efficiently. Whether used in telecommunications, audio processing, or industrial applications, the C6712D remains a reliable and capable solution in the digital signal processing landscape.

Contents

SPRS293A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONS Multichannel Buffered Serial Port Timing Bottom View GDP and ZDP BGA package bottom viewGDP and ZDP 272-PIN Ball Grid Array BGA Package Description Device characteristics Characteristics of the C6712D ProcessorHardware Features Internal Clock C6712D Device compatibility Functional block and CPU DSP core diagram Digital Signal Processor CPU DSP core description ST1 DA1DA2 ST2 Memory Block Description Block Size Bytes HEX Address Range Memory map summaryMemory Map Summary Peripheral register descriptions Emif RegistersL2 Cache Registers HEX Address Range Acronym Register Name Interrupt Selector Registers Device RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name Comments Edma Registers Quick DMA Qdma and Pseudo Registers† PLL Controller Registers Gpio Registers HEX Address Range Acronym Register Name Comments Timer McBSP0 and McBSP1 Registers Signal groups description Clkin CLKOUT3 CLKOUT2† CLKMODE0 Pllhv TMS TDO TDI TCK TrstJtag BIG/LITTLE Endian TOUT1 TINP1 CLKR1CLKS1† Gpio Device Configurations Device configurations at device reset Configuration GDP/ZDP Functional Description PIN BOOTMODE10Emifbe Lendian BIT # Name Description Devcfg register descriptionEksrc Terminal Functions IPD Description Name GDP IPU‡ ZDP PIN SignalTerminal Functions Bootmode BOOTMODE1 C19 BOOTMODE0 C20 IPDEMU1B9 EMU0D9 IPU LITTLE/BIG Endian Format IPD Description Name GDP IPU‡ ZDP Resets and Interrupts Only one asserted during any external data accessEdge-driven Decoded from the two lowest bits of the internal address Emif − Address # Emif − Data # TIMER1 TIMER0IPD Description Name GDP IPU‡ ZDP Emif − Data # Multichannel Buffered Serial Port 1 McBSP1 Reserved for Test Multichannel Buffered Serial Port 0 McBSP0GENERAL-PURPOSE INPUT/OUTPUT Gpio Module IPD Description Name GDP IPU ZDP RSV IPURSV IPD Additional Reserved for Test SPRS293A − October 2005 − Revised November Name GDP ZDP Supply Voltage Pins See the power-supply decoupling portion of this data sheetDvdd Cvdd Description Name GDP ZDP Supply Voltage Pins Ground PinsVSS GND Signal Name PIN GDP ZDP TYPE† VSS GND Description GDP Name ZDP Ground Pins VSS Hardware Development Tools Development supportSoftware Development Tools Fully qualified production device Device supportDevice and development-support tool nomenclature Temperature Range Default 0C to 90C PrefixDevice Family Technology Documentation support CPU CSR register description Revision IDPwrd PCC DCC Pgie GIE PCC CPU CSR Register Bit Field DescriptionCPU ID L2MODE Cache configuration Ccfg register descriptionCcfg Register Bit Field Description DSP Interrupt Default Selector Module Control Interrupt sources and interrupt selectorDSP Interrupts Interrupt Selector Event Edma Selector Edma module and Edma selectorEdma Channels ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0C PLL and PLL controller PLL Lock and Reset Times Clkout Signals, Default Settings, and ControlEnabled or Disabled MIN TYP MAX Unit GDP 150and ZDP Clock SignalPLL Clock Frequency Ranges†‡ Pllcsr Register 0x01B7 C100 PLL Control/Status Register Pllcsr Pllm Register 0x01B7 C110 PLL Multiplier Control Register Pllm DxEN OD1EN OSCDIV1 Register 0x01B7 C124Oscillator Divider 1 Register OSCDIV1 DIR General-purpose input/output GpioGP7 GP6 GP5 GP4 GP2 Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1 Power-supply sequencing Characteristics of the Power-Down ModesPower-supply design considerations System-level design considerations Power-supply decoupling Supply Schottky Diode Core SupplyGND Dvdd C6000 Ieee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif Speed Emif big endian mode correctness BootmodeReset Emif Data Lines Pins Where Data Present IOH Recommended operating conditionsMIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX Unit IOZ Signal transition levels Parameter Measurement Information42 Ω Vref = 1.5 AC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max Ground Timing parameters and board routing analysis Output from DSP Control Signals † Output from DSPBoard-Level Timings Example see Figure See Figure Input and Output ClocksTiming requirements for CLKIN†‡§ Timing requirements for ECLKIN§ see Figure Clkin CLKOUT3 MIN Eclkin Eclkout Asynchronous Memory Timing Timing requirements for asynchronous memory cycles†‡See −Figure Are Setup = Strobe = Not Ready Hold = CE30 BE10 EA212ED150 Read Data AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Ardy AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy CEx BE30 EA212ED310 SYNCHRONOUS-BURST Memory Timing Unit MIN MAX CE30 BE10 BE1 BE2 BE3 BE4EA212 ED150 ARE/SDCAS/SSADS † AOE/SDRAS/SSOE † AWE/SDWE/SSWE† 150 Synchronous Dram TimingTiming requirements for synchronous Dram cycles† see Figure AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Read EclkoutEA2113 Bank EA112 Column EA12 ED150 Write Eclkout EA2113EA12 ED150 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Actv Eclkout CE30 BE10 EA2113 Bank Activate EA112 Row Address EA12 ED150AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab Eclkout Deac Eclkout CE30 BE10 EA2113EA112 EA12 ED150 Refr Eclkout MRS Eclkout CE30 BE10 EA212 MRS value ED150 HOLD/HOLDA Timing Timing requirements for the HOLD/HOLDA cycles† see FigureHold Hold Holda Busreq Timing Eclkout Busreq CLKMODE0 = Reset TimingTiming requirements for reset†‡ see Figure Phase Emif Z Group † Emif Low Group † Boot and Device EXTINT, NMI External Interrupt TimingTiming requirements for external interrupts† see Figure Multichannel Buffered Serial Port Timing Timing requirements for McBSP†‡ see Figure Parameter Clks Clkr FSR intBitn-1 Clkx Timing requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave Unit MIN MAX Bit Bitn-1 Parameter MASTER§ Slave Unit MIN MAXClkx FSX McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Multichannel Buffered Serial Port Timing McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = TINPx TOUTx Timer TimingTiming requirements for timer inputs† GPIx GPOx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingTiming requirements for Gpio inputs†‡ Unit MIN MAX TCK TDO TDI/TMS/TRST Jtag TEST-PORT TimingTiming requirements for Jtag test port see Figure Package thermal resistance characteristics Thermal resistance characteristics S-PBGA package for GDPThermal resistance characteristics S-PBGA package for ZDP Mechanical Data Orderable Device Status Package Pins Package Eco Plan Packaging InformationMSL Peak Temp Qty GDP S-PBGA-N272 Seating Plane 4204396/A 04/02 ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02 Important Notice

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

SYNCHRONOUS DRAM TIMING (CONTINUED)

MRS

ECLKOUT

CE[3:0]

BE[1:0]

EA[21:2]

MRS value

ED[15:0]

AOE/SDRAS/SSOE†

Figure 36. SDRAM MRS Command

TMS320C6712D specifications